Table of contents

A new two-dimensional self-consistent Monte Carlo simulator including multi sub-band transport in 2D electron gas is described and applied to thin-film SOI double gate MOSFETs. This approach takes into account both out of equilibrium transport and quantization effects. Our method allows us to significantly improve microscopic insight into the operation of deep sub-100 nm CMOS devices. We compare and analyse the results obtained with and without quantization effects for a 15 nm long DGMOS transistor.

A diamond based heterostructure diode containing a p-type doped diamond active layer and an n-type doped ultra-nano-crystalline top layer has been investigated. Analysis suggests that the configuration is that of a merged diode, containing two areas of different interfacial barrier potentials in parallel related to the ultra-nano-crystalline grains and the grain boundaries, respectively. Thus this heterostructure may be ideally suited to combine low forward losses with high blocking voltages in diamond high power rectifiers.

In this paper we investigate the reduction in leakage components of a fully depleted (FD) nano-scale double-gate (DG) MOSFET architecture. We have developed a numerical model for a parallel connected hetero-material double-gate (PCHEM-DG) MOSFET followed by gate-controlled band-to-band tunnelling leakage and gate leakage currents in a device having a gate length of 10 nm, and we have observed a reduction in the leakage components compared to bulk MOSFETs. Various leakage current components have been discussed and their variations with respect to bias and device parameters are presented. The results have been compared and contrasted with a MINIMOS 6.0 standard device simulator for the purpose of validating the results. A dramatic increase of the gate leakage and band-to-band tunnelling (BTBT) leakage in nanoscale devices drastically increases the total leakage power in a logic circuit. The PCHEM-DG MOSFET proposes to reduce this power dissipation. This work provides a simple and intuitive method for lowering leakage currents which could be very salutary for future nano-scale device technologies.

Based on 3D simulations, we report a performance assessment of triple- and double-gate FinFETs for high performance (HP), low operating power (LOP) and low standby power (LSTP) logic technologies according to ITRS 65 nm node specifications. The impact of spacer width, lateral source/drain doping gradient, aspect ratio, fin thickness and height along with gate work function on the device performance has been analysed in detail and guidelines are presented to meet the ITRS projections. The design guidelines proposed for a 65 nm node are also examined for a 45 nm node for triple- and double-gate FinFETs. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimized to achieve low values of intrinsic delay. FinFETs should be designed with a higher aspect ratio (∼4) along with lower values of fin thickness to achieve ITRS targets for off-current and intrinsic delay. Triple-gate FinFETs show greater design flexibility in selecting important technological and device parameters as compared to double-gate devices. A design window is presented to achieve ITRS targets for the three logic technology requirements with triple- and double-gate FinFETs.

Semi-classical Monte Carlo simulation is used to study the electrical performance of 18-nm-long n-MOSFETs including a strained Si channel. In particular, the impact of extrinsic series resistance on the drive current I_on is quantified: we show that the large on-current improvement induced by the strain is preserved, even by including an external parasitic resistance. The importance of ballistic transport is also examined and its influence on I_on is highlighted.

In this paper, we present a semiclassical kinetic approach to tunnelling through potential barriers, which can be applied to the simulation of planar semiconductor devices. The proposed model includes thermionic emission currents at the metal–semiconductor interface as well as tunnelling currents together with the effect of barrier lowering. The considered scattering mechanisms are electron–phonon and electron–impurity interactions. The numerical scheme used is a combination of multicell methods with high-order shock-capturing algorithms. To demonstrate the applicability of the developed method, we present the characteristics of several silicon based Schottky barrier diodes.

The mapping of crystalline defect density on the whole area of a 10 × 10 cm² multicrystalline silicon (mc-Si) wafer is a long and difficult task if one uses the conventional techniques of chemical delineation followed by optical or electron microscopy. We have demonstrated the feasibility of a new procedure which proved less time consuming and well adapted to mc-Si wafer quality test automation. This new method is based on the measurement of the sheet resistance variation resulting from defective zones etched by a chemical which is sensitive to crystalline defects. Previously, with special process experimentation, we have shown that the best sensitivity to extended crystalline defects in mc-Si material is supported by 'Secco etch'. This chemical sensitivity to crystalline defects was applied to the development of a new technique for dislocation and defect density mapping. Using an automated four-probe test bench, we have extracted the sheet resistance variation mapping of an mc-Si wafer before and after Secco etching. We have successfully correlated this mapping to the physical image of crystalline defect density and grain boundaries distribution on the whole mc-Si wafer.

We study oxidation-induced redshifts in the energy gap for spherical Si_30, Si₄₂, Si₈₇, Si₉₉, Si₁₆₇ and Si₁₉₁ dots (of 1–2 nm in diameter) passivated with hydrogen by self-consistent calculations using the extended Hückel-type nonorthogonal tight-binding method for three different oxygen configurations (double-bonded, backbonded and inserted). While the nature of the lowest unoccupied molecular orbital (LUMO) state does not depend significantly on the dot size, the highest occupied molecular orbital (HOMO) state is associated closely with oxygen in the Si₁₆₇ or smaller Si dots, and has a much larger Si contribution in the largest Si₁₉₁ dot, so that the HOMO energy in the Si₁₆₇ or smaller Si dots depends significantly on the oxygen configuration, while that in the Si₁₉₁ dot does not. We find that the HOMO–LUMO energy gaps calculated for these Si dots double-bonded to oxygen are all dipole allowed, but gradually decrease from 2.2 eV to about 1.7 eV with increasing dot size, while the inserted oxygen configuration does not cause a significant energy-gap redshift even in the smallest Si dot. Finally, it is found that the energy gaps calculated for the Si dots backbonded to oxygen coincide well with luminescence redshifts observed in porous Si.

We report a method for obtaining thin films of arsenic sulfide by chemical bath deposition and the subsequent formation of InAs by heating the films with a vacuum-deposited coating of In. X-ray diffraction (XRD) studies have shown that the thin film deposited from chemical baths of pH ∼2, prepared by mixing aqueous acidic solutions of As(III) with sodium thiosulfate, is a composite film of crystalline As₂O₃ and As₂S₃, with the incorporation of sulfur. When heated at 150–250 °C, the As₂O₃ component transforms to As₂S₃, but still with very few identifiable peaks in the XRD patterns of the annealed samples. The films have a direct band gap of ≈2.7 eV (as-prepared) and ≈2.52 eV (heated at 250 °C), with forbidden optical transitions. The sheet resistance of the film (300 nm thick) is 10¹² Ω, and the electrical conductivity is 10⁻⁸ Ω⁻¹ cm⁻¹. After being heated in a sulfur-rich atmosphere at >200 °C, the films show photosensitivity. The As₂O₃/As₂S₃ thin film with an evaporated indium film, when heated at 250 °C in nitrogen or air, produces InAs as a major crystalline component. In this case, In₂S₃ or In₂O₃ may be present as a minor component in the films, depending on whether heating is done in nitrogen or air, respectively. The optical band gap of this InAs component is direct, 0.5 to 0.8 eV, depending on the film thickness and heating process. These composite films are photosensitive; a dark conductivity of 0.05 Ω⁻¹ cm⁻¹ in the films formed in nitrogen is ascribed to InAs and 5 Ω⁻¹ cm⁻¹ in the films formed by heating in air is ascribed to the In₂O₃ component. The photoconductivity of the films is of the same order of magnitude as the dark conductivity in each case.

Photoreflectance spectra of AlGaAs/GaAs/AlGaAs wide quantum wells doped by Si up to N_d = 2 x 10¹⁸cm^-3 were investigated at room temperature. Three kinds of spectral peculiarities were observed in photoreflectance spectra: a spectral line due to the GaAs band gap (1.42 eV), short-period Frantz–Keldysh oscillations originating from the barrier band gap (1.71 eV) and lines of subbands in the quantum well. The energies of optical transitions are determined by means of the least-squares approximation of experimental data by the sum of Aspnes relations. The experimental results are in good agreement with the self-consistent subband structure calculation. It is shown that with an increase of the doping level the energies of the interband transitions in the quantum well are changed.

Zirconium oxide (ZrO₂) films have been deposited on Ge-rich SiGe heterolayers at 150 °C by the microwave plasma enhanced chemical vapour deposition (PECVD) technique using zirconium tetra-tert-butoxide. The possible conduction mechanisms in deposited ZrO₂ films have been investigated at both room and high temperature. It is found that the conduction mechanism is dominated by Schottky emission at a low electric field (E < 1.2 MV cm⁻¹). The intrinsic barrier height between Al and ZrO₂ was found to be 0.83 eV. The trap-assisted Poole–Frenkel conduction mechanism is found to take place at a relatively high electric field (E > 1.2 MV cm⁻¹). The extracted trap energy is about 0.78 eV from the conduction band of ZrO₂. It is shown that the current in ZrO₂ films exhibits strong temperature dependence at a low electric field. The trapping behaviour of the charge carriers in thin ZrO₂ gate dielectric stacks during constant gate voltage stress of metal–oxide–semiconductor capacitors has also been investigated.

A new nano-scaled device structure named a quasi-SOI MOSFET is developed for CMOS scaling towards a 25 nm gate length and beyond. The scaling capability and design guidelines of the quasi-SOI MOSFET are comprehensively investigated in this paper. A comparison of physical parameter limitations between the ultrathin body (UTB) SOI MOSFET and the quasi-SOI MOSFET is demonstrated. With careful optimization of device geometry, the specifications with a 25 nm physical gate length for low-operating power (LOP) and high-performance (HP) logic applications can be satisfied by the quasi-SOI MOSFET. The optimal regions for LOP and HP applications are given in this paper, which shed light on the quasi-SOI MOSFET design. Finally, the sensitivity of the nano-scaled quasi-SOI MOSFET and UTB SOI MOSFET to the device parameter fluctuations induced by fabrication variations is discussed.

An intermediate Si layer in Si_1–xGe_x film, replacing the conventionally compositional graded buffer layer, was used to fabricate a relaxed SiGe substrate of high quality. The intermediate Si layer changes the relaxation mechanism of the SiGe thin film via the generation of {3 1 1} dislocation loops. The {3 1 1} dislocation loops are formed in the intermediate Si layer to prompt a state of relaxation in the SiGe overlayer, provide the defects for trapping of threading dislocations (TDs) and leave a SiGe top layer with low dislocation density. For the SiGe/Si/SiGe samples, the residual strain and TDs on the top SiGe layer are independent of the SiGe underlayer thickness. With a 700 nm thick Si_0.8Ge_0.2 overlayer, such a Si_0.8Ge_0.2/Si/Si_0.8Ge_0.2 heterostructure with a smooth surface has a TD density of 8.9 × 10⁵ cm⁻² and 3% residual strain. Owing to the different main relaxation mechanisms in SiGe films, the surface root mean square roughness of this relaxed buffer with a low density of surface pits was measured to be about 3 nm, which is lower than that of the sample without any intermediate Si layer (13 nm). Relaxation of the SiGe overlayer depends on the thickness of the intermediate Si layer. Optimization on relaxation in the SiGe/Si/SiGe structure with an intermediate Si layer of 50 nm is done. Strained Si n-channel metal-oxide-semiconductor field effect transistors with various buffer layers were fabricated and examined. The effective electron mobility for the strained Si device with this novel substrate technology was found to be 80% higher than that of the Si control device. The SiGe thin films with the intermediate Si layer serve as good candidates for high-speed strained Si devices. The global strain in the Si channel with a SiGe/Si/SiGe buffer is still beneficial for short channel devices.

The effects of two different base doping profiles on the current gain and cut-off frequency for all levels of current injection have been studied for NPN Si/SiGe/Si double heterojunction bipolar transistors (SiGe DHBTs). The two-dimensional simulation results for a SiGe DHBT with uniform base doping and a fixed base Gummel number are compared with a non-uniform base doping profile SiGe drift-DHBT device. The study explains the performance of SiGe HBTs at different injection levels by analysing the electron and hole mobility, drift velocity, electric field, junction capacitances and intrinsic and extrinsic base region conductivities. The base doping profile in the SiGe drift-DHBT is controlled in such a way that it creates a net accelerating drift field in the quasi-neutral base for minority electrons. This accelerating field subsequently improves the current gain and cut-off frequency for the SiGe drift-DHBT in comparison with the SiGe DHBT for all levels of injection.

Li-doped p-type ZnO was fabricated by heat treatment of Zn–Li alloy film with 2 at% Li on a quartz substrate in N₂ flow at 500 °C for 2 h, and then in O₂ flow at 700 °C for 1 h. The room-temperature resistivity was measured to be 678.34 Ω cm with a Hall mobility of 1.03 cm² V⁻¹ s⁻¹ and a carrier concentration of 8.934 × 10¹⁵ cm⁻³. Three emission peaks centred at 3.347, 3.302 and 3.234 eV are observed in the photoluminescence spectrum measured at 12 K and are due to neutral acceptor-bound exciton emission, conduction band to acceptor level transition and donor–acceptor pair recombination emission, respectively. The p-type conduction of the Li-doped ZnO may be attributed to the formation of a Li_Zn–N complex acceptor. The optical level of the acceptor is estimated to be about 137 meV. The mechanism of formation of the Li-doped p-type ZnO is discussed in the present work.

Structures combining Si wires and porous Si (PS) were fabricated by a two-step method, in which chemical etching and electrochemical anodization were applied to obtain the silicon wires and PS, respectively. The Si wires can be retained due to the existence of the depletion layer during the electrochemical anodization. The structure of PS connected with silicon wires is attractive to realize effective electric contact on PS.

HgTe/Hg_0.3Cd_0.7Te(0 0 1) quantum well structures fabricated with a Si–O–N insulator layer and an Au top gate electrode exhibit hysteresis effects in their gate-voltage dependent carrier density and thus a nonlinear variation of the Rashba spin–orbit splitting energy (Δ_R). Charging and discharging of states at the semiconductor insulator interface has been found to be responsible for this effect. The quantitative agreement with a simple capacitor model has been used to identify the maximum hysteresis-free gate-voltage range. A nearly linear variation of Δ_R with applied gate voltage has been observed in this range.

The program and erase injection current characteristics of a NROM with SiO₂, HfO₂, LaAlO₃ and Al₂O₃ as the tunnel dielectric, respectively, are studied in this paper. Due to the lower electron and hole energy barriers introduced by LaAlO₃, both the program and erase injection current densities of the NROM using LaAlO₃ as the tunnel dielectric are increased dramatically. The injection efficiency is also improved significantly, which indicates that the introduction of LaAlO₃ can lower the operation voltage of NROM cells. We show that the bit line voltage can be reduced to 3 V for both program and erase operations of NROM cells with LaAlO₃ of 5 nm and 8 nm equivalent oxide thickness (EOT). This can greatly reduce the additional circuits to generate high voltages in a nonvolatile memory chip, meanwhile maintaining sufficient program/erase (P/E) performance and reliability. Our study also shows that the drain disturb is alleviated during programming and erasing the NROM cell with the LaAlO₃ tunnel dielectric due to the lower operating voltages (V_BL = 3 V). Hence a low-voltage low-power NROM flash memory device operation can be achieved by using LaAlO₃ as the tunnel dielectric, due to the enhancement of the P/E injection current.

The etch rate of AlGaInP-based laser structures and selectivity, with respect to SiO₂, are reported as a function of inductively coupled plasma (ICP) process parameters for a BCl₃/Cl₂ etch chemistry. At room temperature InCl₃, a reaction product of In in this environment, is involatile, whereas the products of etching SiO₂ are relatively volatile resulting in low selectivity (∼4:1). Temperature is the most important variable for improving etch rate and selectivity. At 190 °C it is possible to obtain an etch rate up to 0.7 µm min⁻¹ and a selectivity as high as 17:1. It is shown that increasing the ICP power increases the etch rate of AlGaInP but decreases the selectivity, whereas increased reactive ion etching (RIE) power results in improved etch rate and selectivity. The etch rate is also found to be higher at lower chamber pressures although again with little or no change in selectivity. These results are consistent with an AlGaInP etch rate that is dependent on both dc bias and ion flux, in contrast to a SiO₂ etch mechanism that is relatively independent of dc bias but strongly dependent on ion flux. With total gas flow kept constant the etch rate and selectivity are found to increase with the fraction of Cl₂ present. The addition of Ar to the gas mix does increase the etch rate, reaching a maximum at around 70% Ar, but without any significant effect on selectivity.

Photoelectrical properties of uncoated In(OH)_xS_y and PbS(O) layers deposited by SILAR (successive ion layer adsorption reaction) and of TiO₂/In(OH)_xS_y/PbS(O)/PEDOT:PSS solar cell structures were investigated by spectral surface photovoltage, Kelvin-probe, current–voltage and quantum efficiency analysis. By changing the annealing temperature of In(OH)_xS_y in air between 50 and 350 °C, the band gap of In(OH)_xS_y was tuned between 2.6 and 2 eV while the band gap of PbS(O) remained unchanged at about 0.7 eV. The open circuit voltage of the solar cell structures correlated well with the band gap and the workfunction of the In(OH)_xS_y. Surprisingly, excess charge carriers generated in the PbS(O) layer do not contribute significantly to the short circuit current. A short circuit current of more than 10 mA cm⁻² was reached by modifying TiO₂ with Nb. Possible ways of optimization are discussed.

The low-temperature steady-state and time-resolved photoluminescence (PL) from self-assembled InAs quantum dots (QDs) embedded in AlAs with various densities of growth-induced defects has been studied. In contrast to the system of InAs/GaAs QDs, a drastic decrease of the QD PL intensity and decay duration with the formation of relaxed dislocated clusters was observed. It is shown that this strong difference in the luminescence properties of the InAs/GaAs and InAs/AlAs QD systems arises from the very large exciton lifetimes in InAs/AlAs quantum dots, which are longer than the energy transfer time from the QDs to the nonradiative recombination centres of the dislocated clusters.

N-type hydrogenated nanocrystalline silicon (nc-Si:H) films were deposited by the plasma-enhanced chemical vapour deposition (PECVD) technique on p⁺-type crystal silicon (c-Si) substrates; then a kind of heterojunction structure of (n)nc-Si:H/(p⁺)c-Si was obtained. Both negative resistance in forward current–voltage (I–V) measurements and current staircases in reverse I–V experimental curves were observed from this heterojunction of (n)nc-Si:H/(p⁺)c-Si at 77 K. It was verified by the electrical experiments that this structure is a semiconductor heterojunction tunnelling diode. The forward current was considered to be dominated by interband tunnelling, excess and thermionic emission component. Within the reverse bias ranging from around 0 to −13 V, the reverse leakage current can be attributed to minority carriers instead of majority carriers tunnelling across the depletion layer of the heterojunction. By increasing the reverse applied voltage from about −13 V to −37 V, the reverse current can be ascribed to the injection of electrons via sequent resonant tunnelling through the Si nanocrystals quantum dots into the substrate. By further increasing the reverse bias, the reverse current can be assigned to carrier avalanche multiplication within the amorphous buffer layer in the depletion region to enhance the electron resonant tunnelling in the nc-Si:H layer. The results indicate that the (n)nc-Si:H/(p⁺)c-Si structure is a promising candidate for digital circuit applications.

This investigation proposes the improved double δ-doped InGaP/InGaAs heterostructure field-effect transistor (HFET) grown by metalorganic chemical vapour deposition. The extrinsic transconductance (g_m) and saturation current density (I_max) of the double δ-doped InGaP/InGaAs HFET are superior to those of the previously reported single δ-doped InGaP/InGaAs HFETs. The first n-InAlGaP/GaAs HFET is also investigated because it has a high Schottky barrier, a large high band gap and a large conduction-band discontinuity (ΔE_C). Even without indium in the channel of the InAlGaP/GaAs HFET, g_m and I_max are as high as 170 mS mm⁻¹ and 410 mA mm⁻¹, respectively. The g_m values of these two HFETs remain large even when the gate voltages are positive. Moreover, the breakdown voltages of the two examined HFETs both exceed 40 V.

In this paper, we report the first liquid phase epitaxial growth of InAs epitaxial layers using 100% Bi solvent. At a growth temperature of 470 °C, the layers are macroscopically mirror like and the obtained growth rate is ∼40 nm min⁻¹. High-resolution XRD measurements reveal perfect lattice matching between the layer and the substrate, very good structural quality of the layers and less than 0.07% content of substitutional Bi in the layer. Raman spectra from background-doped layers are indicative of carrier concentration near the epilayer surface of less than 10¹⁶ cm⁻³, while assessment of these layers by means of infrared reflectance spectroscopy points to carrier concentration in the bulk of the layers of the order of 1 × 10¹⁵ cm⁻³. 4 K photoluminescence spectra from the same layers exhibit excitonic lines with half-widths ⩽3 meV, which is a signature for electron concentration comparable to the known critical Mott density in InAs of ∼5 × 10¹⁴ cm⁻³. We attribute the low background doping of the epitaxial layers to the low dissolution in Bi of Si and other residual impurities at 470 °C.

We report Monte Carlo simulations of electronic noise in heavily doped nanometric GaAs Schottky-barrier diodes (SBDs) recently proposed as promising devices for THz applications. We consider a SBD operating in series with a parallel output resonant circuit when a high-frequency large-signal voltage is applied to the whole system. Significant modifications of the noise spectrum with respect to the diode subjected to a constant applied voltage are found to occur in the THz-region. To interpret such behaviour, we have developed a simple analytical approach based on the static I–V and C–V relations as well as on the series resistance of the SBD.

If split-gate devices are to be used in practical applications, such as metrology, the ability to fabricate devices with closely identical electronic properties is essential. The alternative is to treat each device as a one-off, and undertake extensive calibrations as a prelude to use. In this paper we describe initial results using standard processing technologies of the electrical performance of split-gate transistors fabricated at the same time, using the same process schedule. The yield and wide variation in electronic properties indicate that new processes will be needed if split-gate transistors are ever to be considered manufacturable.

A set of model equations in the framework of the hydrodynamic approach is set up to describe the longitudinal charge carrier transport in ac-driven ZnS:Mn thin-film electroluminescent structures. Band-to-band impact ionization and a single type of hole recombination centres are taken into account to model charge carrier generation and recombination in the ZnS:Mn layer. The influence of the electric-field dependence of the impact ionization coefficients is analysed by comparing different models for this coefficient which have been used in the literature. Extensive numerical simulations within the framework of the drift-diffusion approach are presented. The main focus is on the average current–voltage characteristic and its dependence on several parameters such as the frequency of the driving voltage or geometry parameters of the ZnS:Mn layer. By comparing the results with those obtained within a hydrodynamic model it is found that, although very high carrier temperatures are reached, the longitudinal transport behaviour is similar in both models. The reason for this is the dominance of the longitudinal drift currents compared to diffusion and temperature-induced currents. The results are in good agreement with experiments. In contrast to simplified transport models which have been used previously the model equations formulated in this paper can be applied to describe the behaviour in thin-film structures with spatially extended contact areas exhibiting lateral pattern formation in certain parameter ranges.

This paper reports a photoelastic waveguide caused by a thin-film composite structure, which is composed of a 20 µm wide stripe window opened in a 110 nm thick W_0.95Ni_0.05 compressively strained thin film and a 4 µm wide W_0.95Ni_0.05 thin-film stripe located at the centre of the window. By calculating theoretically stress field profiles and dielectric constant variations induced by the thin-film composite structure in InGaAsP/InP double heterostructures, it is found that the increase of dielectric constant at 1 µm depth underneath the W_0.95Ni_0.05 thin-film stripe and the decrease of dielectric constant at the same depth underneath between the stripe edge and the window edge have maximal values of 0.0649 and 0.0622, respectively. The waveguide strength is determined to be 1.27 × 10⁻¹–2.85 × 10⁻² in the depth range 1.0 to 3.0 µm of the semiconductor. In comparison with an individual W_0.95Ni_0.05 thin-film stripe or narrow stripe window, the photoelastic waveguide caused by the W_0.95Ni_0.05 thin-film composite structure displays much better waveguide structural characteristics.