Table of contents

The advancement of device technology and the growth of the electronics market were intertwined in the past and probably will continue to be in the future. This observation suggests a new approach to predicting the potentials and the limitations of the scaling of MOSFETs using both technological and economic considerations. It is proposed that silicon CMOS technology can serve the electronics needs of at least most of the 21st century. This analysis also provides a backdrop for evaluating the need for unconventional devices. One current effort to develop 25 nm MOSFETs is described. There appear to be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

The position of Ge islands formed on Si substrates by self-assembly can be determined by adjacent lithographically defined features. Islands tend to form near the edges of narrow Si lines defined by oxide isolation and conventional selective Si epitaxial deposition, offering the possibility of forming small device features without fine lithography. Multiple rows of islands can form on wider lines. The alignment is probably caused by easier nucleation on shallow facets; therefore, the position of the Ge islands can be influenced by controlling the shape of the underlying Si surface.

Ge dots are grown on Si(001) substrates pre-covered with 0.05-0.1 monolayers (ML) of carbon. The C pre-deposition reduces the dot size to less than 20 nm at growth temperatures ranging from 450 to 550 °C. In situ scanning tunnelling microscopy (STM) shows that submonolayer C-deposition locally induces c(4 × 4) reconstruction. The reconstruction is assigned to clusters of six C atoms localized in the two topmost atomic layers in between two Si surface dimers. The non-uniform distribution of carbon together with the enhanced surface roughness give rise to the early onset of island formation at Ge coverages as low as 2.5 ML. These islands show intense photoluminescence signals at 4 K. STM and transmission electron microscopy show that the islands are irregularly shaped. No faceting is detected up to coverages of 4 ML. At 5.8 ML of Ge islands with (105) side facets and a (001) top facet are observed.

We investigate Si nanocrystals fabricated by the rapid thermal oxidation (RTO) of an ultrathin chemical vapour deposition (CVD) amorphous Si (a-Si:H) film. It is found from the transmission electron microscope (TEM) observation that the ultrathin RTO film contains Si nanocrystals of around or less than 5 nm in size. The dynamic electrical conduction measurement of the RTO diode structure including the Si nanocrystals reveals novel features such as the N-shaped tunnel current versus gate voltage characteristics and the hysteresis. It is also found that the gate voltages at the first and second current rise are fixed and the current reduction in the fixed time interval is observed at the constant gate voltage. These findings can be explained by the fixed-amount electron charging effect at the Si nanocrystals and the consequent screening effect on the tunnel current flowing through the diode structure.

We present a systematic study on the oxidation properties of Si dots on silicon-on-insulator material. Si dots with diameters varying from 60 down to 10 nm were realized and investigated in a transmission electron microscope. After thermal oxidation at 850 °C for different times the size and shape of the Si dots were analysed using energy-filtering transmission electron microscopy. The results show that the size of the dots is reduced with a reduced oxidation rate on smaller structures and indications for self-limiting effects. Further, the shape of the dots has changed significantly as the oxidation rate on curved surfaces is reduced with respect to planar surfaces. This effect therefore strongly depends on the aspect ratio of the structure.

The device feature size in Si ULSIs has been reduced over the years, and sooner or later we will probably enter the so-called nanoelectronics era. Two nanofabrication technologies, electron-beam lithography and atomic-beam holography, which are expected to play an important role in the coming era, are discussed first. In order to get finer patterns with electron-beam lithography, improvements in the characteristics of organic resists are crucially important. Organic negative resists with a fine resolution have been developed, and a high-quality resist line pattern with a width as small as 7 nm has been successfully formed. A new atom manipulation technique called atomic-beam holography has been proposed for nanofabrication. It enables direct pattern formation on a substrate by passing laser-cooled atoms through a computer-generated hologram. It is expected to be a technique with a fine resolution, reaching the atomic scale, and a high throughput.

Nano-size devices are developed from two standpoints. One pursues the miniaturization limit of MOS transistors: in this context, we discuss the fabrication of MOS transistors with gate length down to 14 nm and their electrical characteristics. The other approach is to explore `breakthrough devices' that utilize quantum effects: single electron devices are one type of such devices. We discuss the operation of an all-metallic single-electron memory cell along with the electrical characteristics of a single-electron transistor made of aluminium.

Intravalley acoustic phonon scattering of electrons in fully quantized systems based on n-type inversion layers on a (100) surface of p-type Si is studied theoretically. The confining potential normal to the Si/SiO₂ interface is modelled by a triangular quantum well. For the confinement in the lateral directions we assume a parabolic potential. The calculations reveal that the anisotropic electron-acoustic-phonon interaction strongly affects the scattering rate and the average scattering angle. The calculated transition rate of electrons from the first excited state to the ground state shows a strong dependence on spatial confinement and lattice temperature, with the longitudinal phonon mode giving the main contribution to the total rate.

In this paper we present simulation results for the doping dependence of the mobility enhancement in surface-channel strained-Si layers grown on relaxed Si_1-xGe_x buffers. Our numerical results show that there is a significant reduction of the mobility enhancement with increasing substrate doping. At first, this result questioned the performance increase in devices based on these novel Si-based heteroepitaxy concepts when scaled to deep-submicron dimensions. However, we find that this is not really a problem since in devices with non-uniform doping profiles, representative of the state-of-the-art technology, significant mobility enhancement is still observed.

A 3D `atomistic' simulation study of random dopant induced threshold voltage fluctuations and lowering in sub 50 nm MOSFETs is presented. The attention is focused mainly on devices with 30 nm effective channel length which represent the expected level of scaling at the end of the Silicon Roadmap. An efficient algorithm, based on a single 3D solution of the Poisson equation and a simplified current continuity equation, is used in the simulations. Large samples of microscopically different devices (typically 200) are used in order to obtain statistically reliable results. The influence of different aspects of the conventional MOSFET design on the threshold voltage fluctuations and lowering are investigated. Results for fluctuation resistant device architectures based on low-doped epitaxial channel MOSFETs are also presented.

Recent calculations of Fowler-Nordheim tunnelling through `crested' (graded) tunnel barriers have indicated that floating-gate structures using such barriers may combine multi-year retention time with nanosecond recharging time. This effect may be used for the implementation of terabit-scalable, non-volatile random-access memories (NOVORAM) and ultradense electrostatic data storage systems (ESTOR) which may revolutionize digital electronics. In particular, if combined with ultrafast rapid single-flux-quantum (RSFQ) logic circuits, the new memory and storage techniques may lead to the development, within a few years, of teraflops-scale desktop computers.

The notion of quantum-dot cellular automata (QCA) as a possible replacement paradigm for conventional transistor-based logic is reviewed. Experiments using metal tunnel structures demonstrating a functional QCA cell are presented. It is shown that single electron tunnelling transistors used as electrometers verify proper switching of the QCA cell. Additionally, we provide evidence for a QCA cell switching frequency of 14 MHz, and a calculated upper limit of more than 5 GHz.

This paper describes the use of low-current-density tunnelling devices to obtain dense low-power (sub-100 nW/bit) compound semiconductor static random access memory (SRAM); this cell power is over two orders of magnitude lower than the best previously demonstrated in III-V materials. This same circuit topology promises orders of magnitude reduction in static power dissipation for silicon memories, assuming a suitable Si-based negative differential resistance device, at sub-pA current levels, is developed.

The concept of low-standby-power tunnelling-based SRAM (TSRAM) is presented in the context of a scaling theory for all memories and a comparison is given across technologies. Experimental results for a 50 nW TSRAM gain cell using ultralow current density (~1 A cm^-2) resonant tunnelling diodes and low-leakage heterostructure field-effect transistors are discussed. We describe a one-transistor TSRAM cell, verify its operation, and discuss merits of TSRAM relative to other memory types. Silicon TSRAM standby power is projected to be lower than that of conventional-style silicon SRAM or DRAM.

The fabrication of silicon-based quantum devices and advanced buried-gate MIS transistors and circuits may require the development of an epitaxial insulating material that is lattice matched to silicon and also bonds with it to minimize interface states. We report the results of a search for new materials based on earlier partial successes with ZnS/Si. This work has identified beryllium chalcogenides as candidates with high stacking-fault energies for defect suppression. Initial growth and characterization experiments on BeTe/Si, a lattice mismatched system, bear out the theoretical predictions, and result in high-quality insulating films with >1 MV cm^-1 breakdown fields. These experiments strongly suggest that lattice-matched BeSe_0.45Te0.55 will be an even more suitable material.

We investigate the influence of space quantization and poly-gate depletion on the inversion layer capacitance C_inv, total gate capacitance C_tot and threshold voltage V_T in scaled Si-MOSFETs. We also present an analytical expression for the total gate capacitance C_tot that uses classical charge description and takes into account the depletion of the poly-silicon gates. Our simulation results suggest that poly-gate depletion influences the magnitude of C_tot more than the quantum mechanical charge description. For the threshold voltage V_T the situation is more complicated; it is significantly affected by both the poly-gate depletion and the quantum effects in the channel.

A silicon single-electron tunnelling (SET) device with an oxidation-controlled narrow channel was fabricated on a silicon-on-insulator substrate. Measurements at liquid helium temperature show the clear Coulomb blockade effects. The Coulomb oscillations of the SET device are successfully transformed to voltage oscillations by combining it with an nMOSFET load. In addition, it is demonstrated that the obtained small voltage signals are amplified with a CMOS inverter operating at room temperature. These results constitute an important step toward the future hybrid Si ULSIs of SET and CMOS devices.

This paper addresses the optimal tracking of piezo-positioners, which are fundamental tools used in high-precision positioning for nanotechnology applications. This high-precision positioning is particularly important as piezo-positioners are increasingly used in high-speed applications like nanostorage of information and nanofabrication. Precision in positioning is lost during high-speed positioning due to motion-induced dynamic vibrations in the system. These vibrations can be compensated for by using an inversion of the system dynamics to find inputs that achieve exact output tracking. Such an inversion-based approach finds the input that exactly tracks a desired output, but the resulting input may exceed available bandwidth or limits on available input amplitudes. An optimal tracking approach is used in this paper to (a) optimize the positioning trajectory, and (b) restrict trajectory to the available bandwidth and saturation limits of the amplifiers (used to apply voltage to the piezo-positioners). The approach is applied to the output tracking of a piezo-positioner and experimental results are presented.

A scanning tunnelling microscope with a gold tip was used to create clusters and form nano-dots, lines and corrals on a clean stepped Si(111) surface by applying a series of bias pulses to the tip-sample tunnelling junction. Nano-dots with diameters as small as a few nm can be realized. By decreasing the distances between nano-dots, it is possible to create continuous nano-lines of a few nm wide and over a few hundred nm long, which can be used as connections between micro- and nano-electronic components. A nano-corral of about 40 nm in diameter formed by many Au dots of a few nm in diameter each was also created on the Si(111) surface. Single electron tunnelling effects through nano-dots were studied and it was found that `Coulomb staircases' can be observed in the I-V (current-voltage) curve at room temperature through an Au tip-Au cluster-Si substrate double junction system.

The possibility of the self-aligned formation of Pd/Pd₂Si/Si nanostructures on a single-crystal silicon substrate is shown. A porous anodic oxide film of Al was used as a mask which determines the size and shape of the nanostructures. A thin Al film was first deposited on the silicon substrate and then transformed in a nanoporous oxide by the well known anodic treatment procedure in a sulfuric acid and water solution. It is shown by atomic force microscopy that nanoscale Pd clusters with diameters equal to the size of pores in anodic Al remain at the surface of silicon substrate after cathode deposition of Pd into the pores, vacuum thermal annealing and chemical etching of the Al₂O₃ mask. In addition, we determine the dependencies of the size and shape of the nanoclusters on the mask formation regimes and the Pd deposition conditions.

We propose a new type of electronic device in which a quantum percolation phenomenon is utilized. We calculate steady-state wavefunctions in random potential systems by the steepest-descent method and made clear the relation between the correlation length of the wavefunction and the concentration and height of the random potentials. We find that the correlation length becomes minimum at an intermediate potential concentration which coincides with the classical percolation point in the case of low potential barriers. In the case of high potential barriers, the correlation length becomes minimum in a higher concentration region because of the decrease in the tunnelling probability of the electron through the random potential clusters. Finally, we investigate the appropriate concentration of random potentials for a switching device and find that the concentration should be 0.6 which is, in fact, the classical percolation concentration.

A metallic nanowire with quantized conductance was fabricated by electrochemically etching a narrow portion of a metallic wire supported on a solid substrate down to the atomic scale. The width of the nanowire was controlled flexibly by etching atoms away or depositing atoms back onto the wire with the electrochemical potential. Using a feedback loop this method can, at will, fabricate a single or an array of long-term stable nanowires with a pre-selected quantized conductance. These stable nanowires may be used in devices as digitized conductors and as sensors that detect chemicals in the air or in solutions. Using the conductance quantization as a feedback, this method may be used to fabricate nanoelectrodes by etching off the last few atoms in the thinnest portion of each nanowire. These nanoelectrodes may be connected to single molecules in molecular devices.

This special issue of Nanotechnology, consisting of papers presented at the 1998 IEEE Silicon Nanoelectronics Workshop, deals with promising silicon-based nanotechnologies, devices and architecture paradigms that may ultimately replace conventional CMOS, as well as the question of when this technology shift might occur. Nanostructure technology has only relatively recently begun to merge with silicon technology. Quantum transport and other mesoscopic phenomena have traditionally been investigated in other materials systems. The ease of fabrication of metal films (in studies of the Aharonov-Bohm effect) and the relatively high mobility and band offsets afforded by III-V materials (utilized in investigating quantum transport in modulation-doped structures) have led to the fact that mostly materials other than silicon have been utilized to study phenomena on the nanoscale. One could argue that nanoscale inversion layers in MOS devices preceded laterally nanofabricated features by decades, but the long phase coherence lengths available at low temperatures in III-V heterostructures helped III-V materials catch the attention of nanotechnologists. However, the existence of a near perfect native oxide gives silicon a great advantage over other materials in terms of its acceptance into the nanostructures community. Silicon dioxide offers several possibilities including embedded nanocrystals in the gate dielectric, devices built on buried oxide layers, oxidation of nanostructures to modify their properties, the possibility of very high tunnelling barriers and likely many others not yet discovered.

The phenomenal success of silicon technology warrants the investigation of its marriage with less conventional nanotechnology. The opinion that conventional CMOS technology will, more or less, fill the needs of the industry for many more decades appears in this special issue along with many papers offering promising alternatives. It is obvious that, by the mere definition of nanotechnology, the two will soon merge. One of two paths will become clearer over the next decade: either nanometer structures will be incorporated simply as very short gates made possible by new or improved manufacturing techniques, or nanotechnology will offer completely new (to silicon) transport phenomena exploited as part of, or as alternatives to, CMOS. Examples of techniques to be watched closely are: resonant tunnelling devices, self-assembly of quantum dots (and other technologies made possible by improvements in epitaxial growth techniques for SiGe and other materials), applications of single electron tunnelling phenomena in both semiconductors and metals, totally new computational paradigms afforded by the charging of quantum dots, and the incorporation of silicon nanocrystals in gate oxides. These are exciting times for the field of nanoelectronics. No doubt, silicon technology will be strongly affected by future innovations in nanotechnology.