We have calculated the minimum chip area overhead, and hence the bit density
reduction, that may be achieved by memory array reconfiguration (bad bit exclusion),
combined with error correction code techniques, in prospective terabit-scale hybrid
semiconductor/nanodevice memories, as a function of the nanodevice fabrication yield and
the micro-to-nano pitch ratio. The results show that by using the best (but hardly
practicable) reconfiguration and block size optimization, hybrid memories with a pitch
ratio of 10 may overcome purely semiconductor memories in useful bit density if the
fraction of bad nanodevices is below
, while in order to get an order-of-magnitude advantage in density, the number of bad
devices has to be decreased to
. For the simple 'Repair Most' technique of bad bit exclusion, complemented with
the Hamming-code error correction, these numbers are close to 2% and 0.1%,
respectively. When applied to purely semiconductor memories, the same technique
allows us to reduce the chip area 'swelling' to just 40% at as many as 0.1% of bad
devices. We have also estimated the power and speed of the hybrid memories
and have found that, at a reasonable choice of nanodevice resistance, both the
additional power and speed loss due to the nanodevice subsystem may be negligible.