A silicon carbide array for electrocorticography and peripheral nerve recording

The fabrication process flow is shown in figure 1. Devices are fabricated on 6" p-type test grade silicon wafers. Wafers are cleaned in a piranha bath at 120 °C for 10 min, followed by a rinse in 18 M$\Omega$ water, immersion in 1:10 HF at room temperature for 1 min, a rinse in 18 M$\Omega$ water and spin drying. A layer of thermal oxide 1 μm thick may be grown by wet oxidation (Tylan furnace, 1050 °C, atmospheric pressure, 3 h) immediately followed by deposition of 700 nm of polycrystalline n-doped silicon carbide by low-pressure chemical vapor deposition [13] (LPCVD, Tylan furnace, 800 °C, 170 mTorr, 30 sccm methylsilane, 15 sccm dichlorosilane, 2 sccm ammonia, 48 sccm H₂, 2.5 h) and then followed by deposition of 500 nm of silicon dioxide by plasma-enhanced chemical vapor deposition (PECVD, Oxford plasma lab100, 1000 mTorr, 1000 sccm N₂, 750 sccm N₂O, 5 sccm 10%SiH₄/Ar, 20 W, 38 min). Recording sites and bondpads are defined by standard photolithography using g-line photoresist (OCG 825 35cs, Fujifilm, Valhalla, NY), with a UV hard bake step to improve selectivity in the plasma etch. Next, the oxide layer is patterned using reaction ion etching (RIE, Lam Research, 70 mTorr, 150 sccm Ar, 10 sccm CHF₃, 40 sccm CF₄, 705 W RF power, 150 s) followed by patterning of the n-SiC by RIE (Lam Research, 12 mTorr, 125 sccm Cl₂, 75 sccm HBr, 100 sccm CF₄, 300 W RF power, 150 W RF bias) and photoresist strip in oxygen plasma. A contact profilometer is used to measure the height of the n-SiC/SiO₂ stack in order to estimate the degree of overetch in the bottom oxide layer and determine the necessary thickness of the upcoming insulating film.

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Just prior to the deposition of the first insulating layer, wafers are cleaned in a piranha bath at $120~^{\circ}$C for 10 min followed by a rinse in 18 M$\Omega$ water and spin drying. A layer of a-SiC is deposited conformally by PECVD (Oxford plasmalab100, 300 mTorr, 500 sccm Ar, 30 sccm CH₄, 7.5 sccm 10%SiH₄/Ar, 25 W–80 W, 1 h 8 min); argon ion sputtering is used to remove any native oxide that may be present on the n-SiC walls. Chuck temperature is held at 350 °C. The thickness of the a-SiC layer varies with the height of the n-SiC recording site and the amount of overetch during patterning of the recording sites; the a-SiC layer is typically between 550 and 1000 nm. To open electrical access to the recording sites, a mask of g-line photoresist and standard photolithography are used with a UV hard bake step of the resist to improve selectivity during plasma etch. The portion of insulating silicon carbide on top of the doped silicon carbide features is plasma etched until the silicon dioxide separating the two types of carbide is exposed (technics-c, 13 sccm SF6, 21sccm He, 200 mTorr, 150 W). After stripping the photoresist in O₂ plasma, the oxide in-between the two types of carbide is etched in a 1:10 HF bath at room temperature. Next, the free standing portions of a-SiC left after the oxide has been etched are removed in a 10min ultrasonic water bath. Then, a patterned metal stack of 150 nm Pt on 5 nm Ti is obtained by standard lift-off process and deposited by electron beam evaporation.

Next, a second layer of insulating a-SiC is deposited by PECVD with the exact same parameters as the first a-SiC layer described above. CF₄ etch followed by argon sputter etch is used to etch any oxide that may have formed on the first a-SiC layer; the vacuum seal is not broken. To pattern this layer, 2 um of g-line photoresist is spun and patterned with standard photolithography techniques and then plasma etched in the same manner as the first a-SiC layer. This time, the a-SiC and the thermal oxide are plasma etched down to the silicon substrate with the SF₆ chemistry described before. At this stage, the electrode fabrication is finished and what follows is the addition of a backing layer and release procedures. We use a backing layer of 4 μm of polyimide PI-2611 (HD microsystems, Wilmington, DE) which is spin coated and cured as recommended by the manufacturer. The outline of the devices and access holes are patterned on the polyimide by oxygen plasma using a hard mask of silicon dioxide deposited by PECVD and g-line photoresist. Devices are released by XeF₂ etching of the silicon that is in direct contact with the thermal oxide; the gas is able to reach the silicon through access holes opened in the backing layer. Once electrodes are released, an HF dip is used to remove the thermal oxide if necessary. Alternative backing layer material can be used provided it is resistant to XeF₂ and HF.

Thin film SiC ECoGs and polyimide ECoGs (used as controls, refer to the supplemental information available at stacks.iop.org/JNE/14/056006/mmedia) were assembled on printed circuit boards (PCB) using anisotropic conductive film (ACF) as previously described [14, 15]. Briefly, ACF 7379 tape (3M science applied to life) was prebonded to the ACF bondpad area of the PCBs using an Ohashi HMB-10 table-top bonder equipped (5 s, 90 kg cm⁻², 90 °C at bond site, blade set to 135 °C), then the bondpads of the ECoGs were aligned to the footprint on the PCB under a microscope and tacked to the tape with a soldering iron. Finally, permanent bonding was done using Ohashi Bonder equipment (30 s, 160 kg cm⁻², 160 °C at bond site, blade set to 235 °C).

Electrolyte interface spectroscopy (EIS) was done with a NanoZ (Tucker Davis Technology, Alachua, Fl) by immersing the recording sites of the ECoGs and the reference wire in $1 \times {\rm PBS}$. Recording sites were electroplated with platinum black (YSI 3140 platinizing solution, Fondriest Environmental, Fairborn, OH) using the NanoZ for 10 s at  −2 μA. EIS was performed before and after electroplating.

All animal experiments were performed in accordance with the University of California-Berkeley Animal Care and Use Committee regulations. Neural recordings from the central nervous system (CNS) and the peripheral nervous system (PNS) were done in adult male Long-Evans rats.

2.3.1. Primary visual cortex.

2.3.2. Sciatic nerve stimulation.

2.4.1. a-SiC film deposition parameters.

2.4.2. Longevity test.

The bottom panel of figure 1 shows confocal images of recording sites embedded in the amorphous silicon carbide at different fabrication stages. The initial doped SiC pillar (700 nm) with the oxide on top (500 nm) are about 1200 nm above the backplane of the wafer (figure 1(b)); the amorphous SiC matches the height of the n-SiC and due to the conformal deposition of the a-SiC the height of the whole structure is still 1200 nm relative to the a-SiC backplane (figure 1(c)). Once a portion of the a-SiC and the PECVD oxide between the n-SiC and the a-SiC are etched, the surface of the n-SiC pillar is exposed and is leveled with the a-SiC backplane. This becomes clearer once the free standing a-SiC on top of the recording site is removed with ultrasound (figure 1(d)). Finally, the metal easily contacts the doped carbide to connect recording sites and bondpads (figure 1(e)).

During the fabrication process, several critical performance test were carried out. First, the lack of etching of the thermal oxide underneath the carbide features demonstrates that the interface between the doped and the amorphous carbide was properly sealed. As a control, recording sites or bondpads that showed defects at the interface due to photolithography errors provided counter examples of a properly sealed interface and were easily spotted during the HF immersions (see the supplementary information). After depositing and patterning the second layer of insulation, the metal traces were completely embedded within the silicon carbide as shown in figure 2(d).

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To demonstrate the applicability of the process to other types of neural probes, two types of arrays were fabricated: microECoG arrays (with designs for rodents and non-human primate), and intracortical arrays (which can be inserted by means of a silicon stiffener and water soluble adhesives as demonstrated by Felix et al [17]). Figure 2(a) shows the four variants of these devices fabricated on a single wafer and figure 2(c) is a close up of the active area of the 64 channel ECoG and the 32 channel intracortical array.

The typical yield of the assembly process was  >60% working channels; channels failed due to a combination of lack of connection between the thin film features and the PCB during ACF bond or lack of connection between the metal trace and the doped SiC due to a height miss match between the doped SiC recording sites (or bondpads) and the insulating carbide which could not be overcome by the thickness of the metal trace. In vitro characterization showed typical EIS performance with impedance at 1 kHz of  ∼30 k$\Omega$ after platinum black electroplating. The baseline noise in the 1 Hz–1 kHz band was 15–37μVrms and  ∼4μVrms in the high gamma band of 60–200 Hz (figure 3). These values are comparable to those reported for silicon planar arrays of similar dimensions [4, 18] and are slightly higher than the noise floor of our own control polyimide electrode arrays (10 μVrms and 3.7 μVrms for the 1 Hz–1 KHz and 60–200 Hz bands, respectively).

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3.2.1. Activity can be recorded in the primary visual cortex.

A 64 channel SiC ECoG was used to measure the neural responses of the rat primary visual cortex (V1) to visual stimuli that consisted of sinusoidal gratings moving across a computer screen at various orientations. Figure 4(a) shows the location of the active area of the array in V1. Increases in the gamma-band activity were observed in all of the stimulation trials, and some electrodes recorded apparent orientation-tuned responses. Figure 4(b) shows the neural response recorded in one channel during a period of stimulation of bars in the $270^{\circ}$ orientation; the green line indicates the onset of stimulation and red line the offset. A significant increase signal power in the gamma and high gamma bands was observed with a delay of about 100 ms. An example of orientation tuning is shown in figure 4(c) where the strongest activity was observed in response to the 270° and 225° stimuli orientations and the least strong response for 45° and 180°. In the macro scale, neural responses were distributed along the cortex as shown in figure 4(d). As expected, the control stimuli fail to elicit a neural activity in response to the onset of the stimulation; this is shown in figure 4(e). Activity seen in some of the channels during the control trial is outside the stimulation window.

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Recordings from a polyimide ECoG control array are included in the supplemental material.

3.2.2. Compound action potential can be recorded in peripheral nerves.

Figure 5 shows the peripheral nerve response to electrical stimulation of the biceps femoris muscle ipsilateral to a SiC array. The active area of the array was wrapped around the proximal sciatic nerve as shown in figure 5(a). Electrical pulses with different amplitudes were applied to elicit the expected sigmoidal recruitment response curve. Figure 5(b) shows the recorded response to each of the amplitudes tested and figure 5(c) shows a summary of the response of the sciatic nerve as the amplitude of the electrical stimulation increases. For low stimulation amplitudes, 0.5 mA and 0.6 mA, the average peak-to-peak amplitude of the combined action potential was the smallest, and this amplitude rapidly increased for amplitudes of 0.7 to 0.9 mA and saturated at around 1 mA. Figure 5(d) shows the nerve response for measured channels during 0.8 mA stimulation. When electrical stimulation was applied to the muscle contralateral to the array, no action potential was observed regardless of the amplitude of the stimulation.

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Over 50 different films of PECVD a-SiC on silicon wafers were subjected to room temperature and accelerated aging (96 °C) leakage current tests (see Methods). Films less than 150 nm thick were aged up to 24 h while films thicker than 150 nm were aged for up to 1600 h. Every a-SiC film that was subject to the aging test remained visually intact regardless of the length of the experiment; the color of the exposed film was indistinguishable from the control film. In contrast, thermal oxide control samples were clearly etched and in some cases the silicon carrier was completely exposed. Representative optical photographs of this visual inspection are shown in figure 6(a).

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Film thickness measurements by ellipsometer of films up to 130 nm thick showed a change in film thickness of less than 5 nm for all films aged up to 110 h and less than 2 nm for films aged for up to 24 h. A 450 nm SiC that was aged for 280 h had no observable etched material as evidenced in the SEM image shown in figure 6(a) (the portion of the film covered by PDMS is of the same thickness as the portion of the film exposed to the solution; film thickness was measured by micro-spectrophotometry to confirm the lack of etched material). Thermal oxide films etched at rates of 70 nm d⁻¹–150 nm d⁻¹.

Leakage current data for thin (100–117 nm) a-SiC films are shown in figure 6(b); the leakage currents were  <500 nA cm⁻² at  ∼96 °C for the entire duration of the experiment while leakage currents for the control samples increased rapidly within 3 h up to about 2.5 μA cm⁻². When the temperature was dropped from  ∼96 °C to room temperature, leakage currents returned to low levels (50 to 100 nA cm⁻² or 2×  the original room temperature value before testing began). In contrast, room temperature leakage for controls (100 nm thermal oxide) went from  <1 nA cm⁻² to 1 μA cm⁻². Thicker a-SiC films (360 nm and 450 nm) were aged for several days and performed better than how thermal oxide controls would: leakage currents for the 360 nm film started at about 13 nA cm⁻² at 3.24 V and  ∼96 °C and remained about this value for up to 24 h at which point the current steadily increased for a couple of hours to a value greater than 30 nA cm⁻². After 60 h of aging, leakage currents of this a-SiC film was about 70 nA cm⁻² at 96 C while the current at room temperature after over 100 h of aging was as low as 33 nA cm⁻². A thermal oxide film 360 nm thick would have been expected to fail at about 60 h of aging. The 450 nm a-SiC film had a similar trend while exhibiting longer lasting insulating properties: leakage currents at high temperature remained below 50 nA cm⁻² for up to 90 h, longer than the expected failure time of a 450 nm thermal oxide film. This a-SiC film had leakage currents below 100 nA cm⁻² for up to 140 h at which point currents rose rapidly during the following 10 h and then continued to increase at a slower rate for the next several days reaching a maximum of about 500 nA cm⁻² at high temperatures. Finally, 1000 nm a-SiC films deposited on n-type silicon carrier remained good insulators maintaining leakage currents of less than 1 nA cm⁻² at high temperatures for up to 1600 h while the 1000 nm thermal oxide fails at  ∼200 h as shown both by Fang et al [19] and linear interpolations of our own data (observed failure times for 100, 180 and 850 nm thermal oxide films).

XeF₂ etching of samples that failed in the aging process during the first few days showed point defects in the a-SiC films. However, the number of point defects on a section of SiC film exposed to PBS was comparable to the number of point defects in the section of the film outside the PDMS chamber, indicating that the accelerated aging likely did not produce more pinholes.

Etch rates of as-deposited PECVD a-SiC films in XeF₂ were highly dependent on the deposition parameters, but in most cases XeF₂ selectivity to Si over SiC was excellent, and even selectivity of thermal oxide over SiC was good. Typical etch rates of a-SiC films were 0.5 nm min⁻¹ with an estimated Si:SiC selectivity of at least 2500:1. Some a-SiC had etch rates as low as 1 nm h⁻¹ and for one particular recipe there was no measurable change in film thickness after 2 h of exposure to XeF₂. In addition, LPCVD SiC and PVD SiC did not etch in XeF₂.

A desired characteristic of neural probe fabrication processes, especially those used in research, is low process complexity: this greatly improves throughput and yield and encourages wide adoption. Previous approaches to solving the neural probe lifetime problem are potentially less attractive due to process complexity. For example, the use of atomic deposition layers (ALD) is time consuming and expensive (and almost always relies on non-ALD layers for a functional system, as in the alumina/parylene-c bilayer process [20]). Transferred films, as demonstrated by Fang et al, are an effective solution for millimeter scale devices; however, further patterning of the transferred films is often very difficult and more importantly, lateral miniaturization of devices is not possible as transferred films do not protect sidewalls, an issue which becomes critical for micro-patterned implants.

A few characteristics make the demonstrated process attractive specifically for next-generation neural probes. The process flow allows for the pre-processing of the wafer to further customize recording site roughness, 3D shape or material composition (of particular interest for stimulation electrodes). Similarly, recording sites and bondpads can be easily designed and patterned in a variety of ways. In addition, since the insulating layer is a fast, single deposition step and an additional single step is employed for patterning the electrode outline, there is just one material to etch during device definition. In addition, the handling layer is not limited to polyimide: parylene and polydimethylsiloxane (PDMS) rubber or any material resistant to silicon etchants and silicon dioxide etchants can be used.

Fabrication yield can be improved beyond this first demonstration by optimizing the uniformity of the thin film deposition. In particular, we have improved upon our own recipes and have achieved film uniformity as high as 98% on a 6" wafer. This allows us to reliably match the thickness of the bottom a-SiC to the height of the n-SiC within a few tens of nanometers across the entire wafer.

We have demonstrated that our electrode arrays can be used for both CNS and PNS applications. These acute experiments were informed by the desire to show that SiC devices, and specially SiC insulation, are good enough to capture neural signals of comparable quality to traditional electrode arrays. In the primary visual cortex experiment we were able to easily observe neural activity in response to visual stimuli in the expected cortical regions. The signal quality in the SiC electrodes is high enough that orientation tuning was clear in some cortical locations. Due to the increasing interest in PNS applications, we show that the flexibility of the SiC electrode arrays allows them to gently and securely wrap around the sciatic nerve and record from multiple sites along the nerve trunk.

Through the accelerated lifetime testing we were able to demonstrate the outstanding properties of silicon carbide. Accelerated aging tests are not typically carried out while applying electrical potentials (as would be the case in actual use); we believe this is a methodological weakness of much (but not all) of the existing literature that focuses on neural probes. In addition, our methods were inspired by the very comprehensive work by Fang et al [19] in which this test was also used to show the limits for most commonly used insulators and demonstrated the excellent capabilities of thermal oxide. Consequently, we compared silicon carbide films side by side to thermal oxide.

The remarkable properties of SiC for high temperature, and highly corrosive environments have mostly been demonstrated for the crystalline or polycrystaline forms of SiC; these properties arise from the highly stable Si-C bond and the stoichiometry of the films. However, PECVD deposition of carbide films presents challenges that involve film composition which are detrimental to the robustness of the material; the nature of the deposition process makes inevitable the incorporation of hydrogen, carbon-hydrogen and silicon-hydrogen chains, all of which are less stable than silicon-carbon bonds and change the silicon-carbon stoichiometry. Even with this limitation, dissolution of silicon carbide during the aging tests was so slow that in most cases film thickness did not change and etch rates in XeF₂ were much slower than those of other silicon-based materials. SiC films of less than 500 nm subject to the longevity tests did experience rising leakage currents after many hours of aging; we believe this occurred due to the creation of pinholes through the SiC matrix as impurities were removed by the solution, exposing the silicon carrier directly to the PBS. In addition, as the film is being deposited, the presence of C-H and Si-H chains may contribute to the creation of voids; this helps to explain the non-zero leakage currents on as-deposited films. The leakage current would be expected to increase during the aging process, as the surface area of silicon under those voids increases due to the dissolution of silicon into the PBS. In fact, the 450 nm SiC film aged for 280 h shown in figure 6(a) had no observable change in thickness but there were a few locations on the film where silicon had been removed under the SiC, leaving free standing portions of SiC. We were able to address both of these limitations by testing a large number of PECVD recipes and optimizing for low impurity content, low pinhole density and high resistivity. A possible future modification to the process is to layer SiC films deposited with different recipes to capture a global optimum. Depositing thicker SiC films was certainly a very effective way of sealing and protecting voids and impurities; a 1 μm film of SiC withstood accelerated aging tests for at least 1600 h maintaining leakage currents below 1 nA cm².

Silicon carbide insulation has outperformed other insulating materials tested in similar accelerated aging tests [19, 20] and lifetime at body temperatures has been estimated to be in the order of decades. Unlike those studies, we have not been able to experimentally determine failure times for silicon carbide films at high temperatures, which makes it impractical to experimentally determine failure times at any temperature lower than our current set up. With this limitation we cannot calculate the estimated time to failure at body temperatures based on the Arrhenius equation, which requires experimental determination of the activation energy for the degradation reactions. Our results suggest silicon carbide will remain stable for several decades; in vivo chronic experiments in animal models will determine the lifetime limits of this technology.

Our fabrication method can also be used to fabricate devices for electrical stimulation. Materials like platinum–iridium can be electroplated on the n-SiC surface to improve the charge injection capabilities of the device. Alternatively, pre-processing of the wafer can be done before deposition of the n-SiC film in order to customize the surface of the active sites. For example, high surface area n-SiC surfaces can be achieved in order to improve charge injection for effective stimulation.