A new digital-analog multiplex method using an adder circuit

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Published 26 March 2015 © 2015 IOP Publishing Ltd and Sissa Medialab srl
, , 10th International Conference on Position Sensitive Detectors Citation Y. Nakamura et al 2015 JINST 10 C03048 DOI 10.1088/1748-0221/10/03/C03048

1748-0221/10/03/C03048

Abstract

In this paper, we propose a new multiplex method for the Time-over-Threshold (ToT) method using an adder circuit to encode channel information in the pulse height. The proposed method is a combination of Multiple-Valued-Logic (MVL) and the ToT method for radiation-detection systems. In order to validate the method, a 12 mm × 12 mm × 12 mm monolithic GAGG crystal was mounted on a 16ch HAMAMATSU MPPC, whose pixel size was 3 mm × 3 mm. The input resistors of the adder circuit were set at 2 kΩ, 4 kΩ, 8 kΩ, 16 kΩ, and so on, and the feedback resistor was set at 1 kΩ. Therefore, the output voltage becomes 1/2, 1/4, 1/8, ⋅⋅⋅, for ch1, ch2, ch3, ⋅⋅⋅, respectively. A 4ch-input multiplex, which corresponds to 16-valued logic, was successfully verified. However, an 8ch-input multiplex corresponding to 256-valued logic was not verified, owing to noise factors such as ringing and overshoot. Therefore, a new decoding algorithm or a noise-cutting circuit is needed.

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10.1088/1748-0221/10/03/C03048