Carrier statistics and quantum capacitance effects on mobility extraction in two-dimensional crystal semiconductor field-effect transistors

Two-dimensional (2D) semiconductor crystals, such as the transition metal dichalcogenides (TMDs), are attractive for atomically thin field-effect transistors (FETs) with no broken bonds [1, 2]. Coupling the electrostatic advantages with appreciable transport properties in these materials indicates a possibility of high-performance device applications [3–5]. As with graphene, the weak interlayer coupling allows TMD individual layers to be isolated and studied. In contrast to graphene, however, the large energy bandgap of 2D semiconductors enables high on/off current ratio FETs [6, 7]. Most properties of interest in FETs originate in the statistics of electrons in the conduction band (CB) and holes in the valence band (VB). The electrostatic field-effect control of these mobile carriers by gates, and their transport properties completely determine the device characteristics. Consequently, the methods employed to extract various parameters from the device characteristics, such as the carrier density and mobility must pay careful attention to the carrier statistics and its link with transport [8]. This has not been done for 2D crystal semiconductors yet. This work presents these fundamental results and identifies a number of errors that arise if the carrier statistics effects are neglected, and provides methods for accurate parameter extractions.

For a single-gate FET with a single-layer (SL) 2D semiconductor channel, the electron density in the channel is usually written as [9]:

$$\begin{eqnarray}&&{{n}_{{\rm ox}}}={{C}_{{\rm ox}}}\left( {{V}_{{\rm gs}}}-{{V}_{{\rm th}}} \right)/q,\end{eqnarray} \tag{ 1 }$$

where ${{C}_{{\rm ox}}}={{\varepsilon }_{{\rm ox}}}/{{t}_{{\rm ox}}}$ is the gate oxide capacitance per unit area, and ${{\varepsilon }_{{\rm ox}}}$ and ${{t}_{{\rm ox}}}$ are the dielectric constant and thickness of the dielectric layer respectively. ${{V}_{{\rm gs}}}$ is the gate voltage, ${{V}_{{\rm th}}}$ the threshold voltage, and $q$ is the electron charge. The gate capacitance ${{C}_{{\rm tot}}}$ in an FET is the total capacitance of ${{C}_{{\rm q}}}$ and ${{C}_{{\rm ox}}}$ connected in series, where ${{C}_{{\rm q}}}$ is the quantum capacitance of the channel [8, 10, 11]. ${{C}_{{\rm tot}}}$ is dominated by the smaller capacitance. Thus equation (1) is only valid when ${{C}_{{\rm q}}}\gg {{C}_{{\rm ox}}}.$ However, for devices with thin high-κ gate dielectrics, or for nondegenerate carrier statistics when the Fermi level is located deep inside the bandgap, ${{C}_{{\rm q}}}$ can be comparable, or even lower than ${{C}_{{\rm ox}}},$ making equation (1) no longer valid. This calls for re-analyzing the carrier statistics and quantum capacitance for TMD channels.

The E–k dispersion of mobile carrier states in 2D semiconductors near the bottom of the CB and the top of the VB in the first Brillouin zone is accurately captured by the parabolic approximation: $E\left( k \right)={{\hbar }^{2}}{{k}^{2}}/2{{m}^{*}},$ where $\hbar$ is the reduced Planck constant, $m*$ is the band-edge effective mass, and $k=\sqrt{k_{x}^{2}+k_{y}^{2}}$ is the in-plane 2D wave vector. The band-edge density of states (DOS) is then given by $g\left( E \right)={{g}_{{\rm s}}}{{g}_{{\rm v}}}{{m}^{*}}/2\pi {{\hbar }^{2}},$ where ${{g}_{{\rm s}}}$ and ${{g}_{{\rm v}}}$ are the spin and valley degeneracy factors respectively. The 2D carrier densities in the CB and VB are accurately decribed as $n=\mathop \int \nolimits_{{{E}_{{\rm c}}}}^{\infty } g\left( E \right)f\left( E \right){\rm d}E$ and $p=\mathop \int \nolimits_{-\infty }^{{{E}_{{\rm v}}}} g\left( E \right)\left[ 1-f\left( E \right) \right]{\rm d}E,$ where ${{E}_{{\rm c}}}$ and ${{E}_{{\rm v}}}$ are the band-edge energies of the CB and VB respectively. The occupation probability is the Fermi–Dirac distribution $f\left( E \right)=1/\left\{ 1+{\rm exp} \left[ \left( E-{{E}_{{\rm f}}} \right)/{{k}_{{\rm B}}}T \right] \right\},$ with ${{k}_{{\rm B}}}$ the Boltzmann constant, $T$ the absolute temperature, and E_f the Fermi level. From above equations, the electron density in the CB is $n={{g}_{{\rm 2D}}}{{k}_{{\rm B}}}T{\rm ln} \left\{ 1+{\rm exp} \left[ \left( {{E}_{{\rm f}}}-{{E}_{{\rm c}}} \right)/{{k}_{{\rm B}}}T \right] \right\}$ and the hole density in the VB is $p={{g}_{{\rm 2D}}}{{k}_{{\rm B}}}T{\rm ln} \left\{ 1+{\rm exp} \left[ -\left( {{E}_{{\rm f}}}-{{E}_{{\rm v}}} \right)/{{k}_{{\rm B}}}T \right] \right\}.$ We make the assumption that the electrons and holes have the same effective masses, which may be relaxed if not appropriate. Under thermal equilibrium, the Fermi energy for n-type TMD layer is thus ${{E}_{{\rm f}}}-{{E}_{{\rm c}}}={{k}_{{\rm B}}}T{\rm ln} \left[ {\rm exp} \left( n/{{g}_{{\rm 2D}}}{{k}_{{\rm B}}}T \right)-1 \right],$ and for p-type it is ${{E}_{{\rm v}}}-{{E}_{{\rm f}}}={{k}_{{\rm B}}}T{\rm ln} \left[ {\rm exp} \left( p/{{g}_{{\rm 2D}}}{{k}_{{\rm B}}}T \right)-1 \right]$.

Figure 1(a) shows ${{E}_{{\rm f}}}$ plotted as a function of temperature for MoS₂ single layers for different 2D carrier densities. The red lines are for n-type and the blue lines for p-type layers. The horizontal dashed line indicates the Fermi level for intrinsic MoS₂; it stays at the mid gap because of the assumed symmetric bandstructure. SL TMDs have large electron effective masses, (∼0.57m₀ for MoS₂, ∼0.6m₀ for MoSe₂, and ∼0.61m₀ for MoTe₂) [12]. As a result, the DOS is high. As shown in figure 1(a), the carrier statistics stays effectively nondegenerate at room temperature over a very wide range of density of interest (10¹¹ ∼ 10¹³ cm⁻²), with the Fermi level hardly entering the bands. As expected, at elevated temperatures the semiconductor turns intrinsic because of interband thermal excitation of carriers. The intrinsic carrier density $\left( {{n}_{{\rm i}}} \right)$ in 2D crystal semiconductors is given by

$$\begin{eqnarray}&&{{n}_{{\rm i}}}=n=p={{g}_{{\rm 2D}}}{{k}_{{\rm B}}}T{\rm ln} \left[ 1+{\rm exp} \left( -\frac{{{E}_{0}}}{{{k}_{{\rm B}}}T} \right) \right],\end{eqnarray} \tag{ 2 }$$

where ${{E}_{0}}={{E}_{{\rm g}}}/2,$ ${{E}_{{\rm g}}}$ is the band gap energy. Since in most 2D semiconductors, ${{E}_{0}}\gg {{k}_{{\rm B}}}T$ [12], ${{n}_{{\rm i}}}$ can be approximated by ${{n}_{{\rm i}}}\approx {{g}_{{\rm 2D}}}{{k}_{{\rm B}}}T{\rm exp} \left( -{{E}_{{\rm g}}}/2{{k}_{{\rm B}}}T \right).$ The intrinsic sheet carrier density is low even at room temperature because of the large bandgap, for example, ${{n}_{{\rm i}}}$ ∼ 1.1 × 10⁻² cm⁻² for SL MoS₂ as compared to ∼10¹¹ cm⁻² for zero-gap graphene [8]. The carrier density in a semiconductor cannot be lower than n_i at that temperature; this is also the reason for the high achievable on–off ratios in TMD FETs compared to 2D graphene.

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The effect of the gate voltage in a FET is to tune the carrier density, and consequently, the Fermi level in FET channels. A positive gate voltage applied to an intrinsic 2D crystal single layer channel populates the CB with electrons, and the Fermi level is driven from the midgap towards the CB edge. The local channel electrostatic potential ${{V}_{{\rm ch}}},$ which is tuned by the gate bias, determines the electron density in the 2D crystal layer:

$$\begin{eqnarray}\begin{array}{lllllllllllllll} n & = & {{g}_{{\rm 2D}}}{{k}_{{\rm B}}}T{\rm ln} \left\{ 1+{\rm exp} \right. \\ {} & {} & \times \left. \left[ -\left( {{E}_{0}}-q{{V}_{{\rm ch}}} \right)/{{k}_{{\rm B}}}T \right] \right\}. \\ \end{array}\end{eqnarray} \tag{ 3 }$$

Writing the total charge density in a 2D semiconductor single layer $Q=q\left( p-n \right)$ as a function of ${{V}_{{\rm ch}}},$ and using the definition of quantum capacitance ${{C}_{{\rm q}}}=-\partial Q/\partial {{V}_{{\rm ch}}},$ one obtains for 2D crystals

$$\begin{eqnarray}&&\begin{array}{lllllllllllllll} {{C}_{{\rm q}}}={{q}^{2}}{{g}_{{\rm 2D}}}\left\{ {{\left[ 1+{\rm exp} \left( \frac{{{E}_{0}}-q{{V}_{{\rm ch}}}}{{{k}_{{\rm B}}}T} \right) \right]}^{-1}} \right. \\ \left. \quad \;+{{\left[ 1+{\rm exp} \left( \frac{{{E}_{0}}+q{{V}_{{\rm ch}}}}{{{k}_{{\rm B}}}T} \right) \right]}^{-1}} \right\} \\ \quad \approx {{q}^{2}}{{g}_{{\rm 2D}}}{{\left[ 1+\frac{{\rm exp} \left( {{E}_{{\rm g}}}/2{{k}_{{\rm B}}}T \right)}{2{\rm cosh} \left( q{{V}_{{\rm ch}}}/{{k}_{{\rm B}}}T \right)} \right]}^{-1}}. \\ \end{array}\end{eqnarray} \tag{ 4 }$$

Figure 1(b) shows the calculated quantum capacitance for SL MoS₂ as a function of ${{V}_{{\rm ch}}}$ at room temperature and 77 K. For intrinsic layers, ${{V}_{{\rm ch}}}$ in the figure also indicates the location of the Fermi level. The electrostatic parallel-plate capacitances ${{C}_{{\rm ox}}}$ (per unit area) for two dielectrics typically used as the gate oxide in TMD FETs: HfO₂ and SiO₂, are shown. Only when the Fermi level is deep inside the CB or VB, when $\left| q{{V}_{{\rm ch}}} \right|\gt {{E}_{0}},$ and the quantum capacitance ${{C}_{{\rm q}}}$ saturates and approaches the degenerate limit: ${{C}_{{\rm q}}}\to {{C}_{{\rm dq}}}={{q}^{2}}{{g}_{{\rm 2D}}}.$ As indicated by the dielectric cases in figure 1(b), for most of the nondegenerate region, ${{C}_{{\rm q}}}$ is much lower than ${{C}_{{\rm ox}}}.$ For very thin dielectrics, for example: 3 nm HfO₂, even the degenerate limit ${{C}_{{\rm dq}}}$ is comparable with ${{C}_{{\rm ox}}}.$ Thus the quantum capacitance can significantly influence the field effect. Device models should include ${{C}_{{\rm q}}}$ in order to properly capture the device behavior, especially in the subthreshold region and for devices with high-κ or thin dielectrics.When the quantum capacitance is taken into consideration, a part of the gate voltage is dropped in the channel to populate it with an electron (hole) density ${{n}_{{\rm ch}}}$ $\left( {{p}_{{\rm ch}}} \right),$ as shown in the equivalent circuit in the inset of figure 2(a). For FETs with intrinsic 2D semiconductor channels, under positive gate bias, the relationship between ${{V}_{{\rm gs}}}$ and ${{n}_{{\rm ch}}}$ is

$$\begin{eqnarray}&&{{V}_{{\rm gs}}}={\underbrace{{{V}_{0}}+{{V}_{T}}{\rm ln} \left[ {\rm exp} \left( \frac{{{n}_{{\rm ch}}}}{{{g}_{{\rm 2D}}}{{k}_{B}}T} \right)-1 \right]}_{{{V}_{{\rm ch}}}}}+{{V}_{{\rm ox}}},\end{eqnarray} \tag{ 5 }$$

where ${{V}_{{\rm ch}}}$ and ${{V}_{{\rm ox}}}$ denote the voltage drops in the channel and the dielectric layer respectively, and ${{V}_{0}}={{E}_{0}}/q,$ ${{V}_{T}}={{k}_{{\rm B}}}T/q$ and ${{V}_{{\rm ox}}}=q{{n}_{{\rm ch}}}/{{C}_{{\rm ox}}}.$ Equation (5) is a transcendental equation, which can only be solved numerically. The resulting ${{n}_{{\rm ch}}}$ in an intrinsic SL MoS₂ channel as a function of ${{V}_{{\rm gs}}}$ from equation (5) is shown in figure 2(a) as black lines for 3 and 300 nm SiO₂ gate oxide. Electron densities calculated with equation (1) are also shown in figure 2(a) as reference with blue lines. The shaded areas and the arrows indicate the error between ${{n}_{{\rm ox}}}$ and ${{n}_{{\rm ch}}}.$ It is obvious that the carrier density can be strongly overestimated by using the commonly used expression equation (1) for ${{n}_{{\rm ox}}}.$ The large deviation proves that neglecting the quantum capacitance will lead to significant errors in the extraction of the carrier density.

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Reducing equation (5) from the transcendental form under common device operation conditions will enable the direct calculation of ${{n}_{{\rm ch}}}.$ At low gate voltages in the sub-threshold region of a FET where ${{C}_{{\rm q}}}\ll {{C}_{{\rm ox}}},$ most of the gate voltage drops in the channel, that is ${{V}_{{\rm gs}}}\approx {{V}_{{\rm ch}}}.$ In this case, the electron density in the channel ${{n}_{{\rm low}}}$ reduces to

$$\begin{eqnarray}&&{{n}_{{\rm low}}}\approx {{g}_{{\rm 2D}}}{{k}_{{\rm B}}}T{\rm ln} \left[ {\rm exp} \left( \frac{{{V}_{{\rm gs}}}-{{V}_{0}}}{{{V}_{T}}} \right)+1 \right],\end{eqnarray} \tag{ 6 }$$

as shown by the green line in figure 2(a). ${{n}_{{\rm low}}}$ arises solely due to the channel material itself, thus is independent of the gate oxide. At high gate voltages when the FET is 'strongly on', ${{C}_{{\rm q}}}$ reaches ${{C}_{{\rm dq}}},$ the channel electron density ${{n}_{{\rm high}}}$ is approximately

$$\begin{eqnarray}&&{{n}_{{\rm high}}}\approx \frac{1}{q}\frac{{{C}_{{\rm ox}}}{{C}_{{\rm dq}}}}{{{C}_{{\rm ox}}}+{{C}_{{\rm dq}}}}\left( {{V}_{{\rm gs}}}-{{V}_{{\rm cr}}} \right),\end{eqnarray} \tag{ 7 }$$

as shown by the red lines in figure 2(a). ${{V}_{{\rm cr}}}$ is the critical gate voltage that differentiates the situations described by equations (6) and (7), which corresponds to the gate voltage when ${{C}_{{\rm q}}}={{C}_{{\rm ox}}}$,

$$\begin{eqnarray}\begin{array}{lllllllllllllll} {{V}_{{\rm cr}}} & = & {{V}_{0}}+{{V}_{T}}{\rm ln} \left( \frac{{{C}_{{\rm ox}}}}{{{C}_{{\rm dq}}}-{{C}_{{\rm ox}}}} \right) \\ {} & {} & +{{V}_{T}}\frac{{{C}_{{\rm dq}}}}{{{C}_{{\rm ox}}}}{\rm ln} \left( \frac{{{C}_{{\rm dq}}}}{{{C}_{{\rm dq}}}-{{C}_{{\rm ox}}}} \right), \\ \end{array}\end{eqnarray} \tag{ 8 }$$

When ${{V}_{{\rm gs}}}\lt {{V}_{{\rm cr}}},$ ${{n}_{{\rm ch}}}$ is determined by equation (6); when ${{V}_{{\rm gs}}}\gt {{V}_{{\rm cr}}},$ ${{n}_{{\rm ch}}}$ is determined by equation (7). The critical carrier density ${{n}_{{\rm cr}}}$ corresponding to ${{V}_{{\rm cr}}}$ is

$$\begin{eqnarray}&&{{n}_{{\rm cr}}}=\frac{{{C}_{{\rm dq}}}{{V}_{T}}}{q}{\rm ln} \left( \frac{{{C}_{{\rm dq}}}}{{{C}_{{\rm dq}}}-{{C}_{{\rm ox}}}} \right).\end{eqnarray} \tag{ 9 }$$

For SL MoS₂ FETs with 300 nm SiO₂ gate oxide, ${{V}_{{\rm cr}}}~\sim ~0.698 V$ and ${{n}_{{\rm cr}}}$ ∼ 1.86 × 10⁹ cm⁻²; for 3 nm SiO₂, ${{V}_{{\rm cr}}}~\sim ~0.818 V$ and ${{n}_{{\rm cr}}}$ ∼ 1.87 × 10¹¹ cm⁻². It is worth noting that equations (3)–(8) are obtained based on the intrinsic material and the assumption of zero flat-band voltage, that is, ${{V}_{{\rm th}}}={{V}_{{\rm cr}}}.$ If a SL MoS₂ is unintentionally doped with n-type impurities (which is typical till date), ${{V}_{{\rm th}}}$ shifts by several tens of Volts toward negative values depending on the impurity density and the gate barrier thickness. In this case, the gate voltage term ${{V}_{{\rm gs}}}$ in equations (6) and (7) should be replaced by ${{V}_{{\rm gs}}}+{{V}_{{\rm cr}}}-{{V}_{{\rm th}}}$.

Now we discuss the validity of using equation (1) to estimate the carrier density in the 2D crystal FET channel. Because equation (1) is valid only when ${{V}_{{\rm ox}}}\approx {{V}_{{\rm gs}}},$ we show the proportions of ${{V}_{{\rm ch}}}$ and ${{V}_{{\rm ox}}}$ in ${{V}_{{\rm gs}}}$ as a function of ${{n}_{{\rm ch}}}$ obtained from equation (5) for SL MoS₂ FETs with 3 and 300 nm SiO₂ dielectric layers in figure 2(b). As can be observed, for FET with 300 nm SiO₂ dielectric layer, ${{n}_{{\rm ch}}}$ ranging from 10¹¹ to 10¹³ cm⁻² can easily be overestimated by equation (1) because V_ox is significantly smaller than ${{V}_{{\rm gs}}}.$ For the very thin 3 nm SiO₂ gate oxide, ${{n}_{{\rm ch}}}$ can be strongly overestimated over the whole carrier density range of interest: 10¹¹ ∼ 10¹³ cm⁻², as also shown in figure 2(b). For thin gate barriers, a significant amount of voltage is dropped in the semiconductor channel because of the carrier statistics, and its neglect can cause large errors.

With the correct carrier statistics, we now re-examine the methods employed to extract other important parameters from the device characteristics, for example, the carrier mobility. A commonly used method to estimate the carrier mobility in the channel is the field-effect mobility ${{\mu }_{{\rm FE}}},$ given by [9, 13–17]:

$$\begin{eqnarray}&&{{\mu }_{{\rm FE}}}=\frac{{\rm d}\sigma }{{\rm d}{{V}_{{\rm gs}}}}\left( \frac{1}{{{C}_{{\rm ox}}}} \right)=\frac{{\rm d}{{I}_{{\rm d}}}}{{\rm d}{{V}_{{\rm gs}}}}\left( \frac{L}{W{{C}_{{\rm ox}}}{{V}_{{\rm ds}}}} \right),\end{eqnarray} \tag{ 10 }$$

where σ is the electronic conductivity in the channel, ${{I}_{{\rm d}}}$ is the drain current, ${{V}_{{\rm ds}}}$ is the drain voltage, and $L$ and $W$ are the length and width of the channel respectively. Equation (10) is widely used in device analysis of Si-based MOSFETs and III-V semiconductor-based FETs. However its validity in TMD devices must be re-examined. Equation (10) is derived from the fundamental drift current equation of an FET in the linear regime at small drain voltages:

$$\begin{eqnarray}&&{{I}_{{\rm d}}}=Wq{{n}_{{\rm ch}}}{{v}_{{\rm d}}}=q\frac{W}{L}{{n}_{{\rm ch}}}{{V}_{{\rm ds}}}{{\mu }_{{\rm d}}},\end{eqnarray} \tag{ 11 }$$

where ${{v}_{{\rm d}}}$ and ${{\mu }_{{\rm d}}}$ are the carrier drift velocity and drift mobility in the channel respectively. To obtain equation (10) from equation (11), the first assumption is that the carrier density in the channel can be calculated using equation (1). For on-state device operation where ${{V}_{{\rm gs}}}\gg {{V}_{{\rm th}}},$ equation (7) captures the carrier statistics and quantum capacitance more accurately. The term ${{V}_{{\rm cr}}}$ or ${{V}_{{\rm th}}}$ can be eliminated by taking the derivative of ${{I}_{{\rm d}}}$ versus ${{V}_{{\rm gs}}}.$ Equation (10) can be recast as

$$\begin{eqnarray}&&{{\mu }_{{\rm FE}}}=\frac{{\rm d}{{I}_{{\rm d}}}}{{\rm d}{{V}_{{\rm gs}}}}\left( \frac{L}{W} \right)\frac{1}{{{V}_{{\rm ds}}}}\frac{{{C}_{{\rm ox}}}+{{C}_{{\rm dq}}}}{{{C}_{{\rm ox}}}{{C}_{{\rm dq}}}},\end{eqnarray} \tag{ 12 }$$

which amounts to replacing ${{C}_{{\rm ox}}}\to {{C}_{{\rm ox}}}{{C}_{{\rm dq}}}/{{C}_{{\rm ox}}}+{{C}_{{\rm dq}}},$ which is not a fundamental new result in itself, but we emphasize that not doing so can cause significant errors. However, another implicit but more important assumption in equations (10) and (12), which is barely discussed, is that the carrier mobility ${{\mu }_{{\rm d}}}$ in the channel does not change when gate bias is varying. The derivative in equations (10) and (12) can lead to significant errors when ${{\mu }_{{\rm d}}}$ is ${{V}_{{\rm gs}}}$ dependent, as we now discuss.Because the carrier density is modulated by the gate bias, the ${{V}_{{\rm gs}}}-dependence$ of ${{\mu }_{{\rm d}}}$ is determined by the dependence of ${{\mu }_{{\rm d}}}$ on the carrier density ${{n}_{{\rm ch}}}.$ Figure 3(a) shows the calculated electron drift mobility in SL MoS₂ as a function of electron density at three different temperatures: 4, 77 and 300 K. The gate dielectric is chosen as 300 nm SiO₂. The mobility is calculated in the relaxation-time approximation of the Boltzmann transport equation. Scatterings by polar optical phonons, deformation potential phonons (acoustic and optical), remote optical phonons from the dielectric layer, and ionized impurities have been taken into consideration. Details of the calculation can be found in [3]. As can be seen from figure 3(a), at all three temperatures, ${{\mu }_{{\rm d}}}$ first increases with ${{n}_{{\rm ch}}}$ and then tends to saturate at high density. At high temperature, a higher carrier density is required to fully screen Coulombic scattering potentials. For example, ${{\mu }_{{\rm d}}}$ starts to saturate at ∼3 × 10¹³ cm⁻² at 300 K, but at ∼4 × 10¹¹ cm⁻² for very low temperature 4 K. Combining the results of figure 3(a) and equation (5), one can obtain the electron mobility as a function of ${{V}_{{\rm gs}}},$ as shown in figure 3(b). An ionized impurity density ${{N}_{d}}$ of 4 × 10¹² cm⁻² is assumed to be located in the channel, which leads to a negative shift of the threshold voltage of ∼55 V from the intrinsic case based on the following relationship: ${{N}_{d}}\approx {{\left( C_{{\rm ox}}^{-1}+C_{{\rm dq}}^{-1} \right)}^{-1}}\left( {{V}_{{\rm cr}}}-{{V}_{{\rm th}}} \right)/q.$ At 4 K, the mobility starts to saturate at $\Delta {{V}_{{\rm gs}}}(={{V}_{{\rm gs}}}-{{V}_{{\rm th}}})~\sim ~10 V,$ while mobilities at 77 and 300 K keep increasing even when $\Delta {{V}_{{\rm gs}}}$ is well over 100 V. Note that the drift mobility ${{\mu }_{{\rm d}}}$ discussed here differs from the Hall mobility ${{\mu }_{{\rm H}}}$ by a Hall factor, which is induced by the magnetic field in the Hall-effect measurement. The Hall factor is often assumed to be unity, however careful consideration of the Hall factor with relevant scattering mechanisms at different temperatures needs further detailed study[18]. Baugher et al [19] have compared ${{\mu }_{{\rm FE}}}$ and ${{\mu }_{{\rm H}}}$ and found that ${{\mu }_{{\rm FE}}}$ can differ significantly from ${{\mu }_{{\rm H}}}.$ They attributed the lower ${{\mu }_{{\rm H}}}$ to the possible screening of charged impurity scattering at higher densities, which is consistent with our results in figure 3. In the following, we quantitatively explain the discrepancy between the conventional method of extracting the field-effect mobility ${{\mu }_{{\rm FE}}}$ and the 'true' drift mobility ${{\mu }_{{\rm d}}}$ in the channel by combining a theoretical transport calculation with density-dependent mobility, and with the correct electrostatics of the FET incorporating the correct carrier statistics and quantum capacitance. This final analysis explains the measured experimental behavior of SL TMD FET, and highlights the problems with conventional models of mobility extraction.

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Figure 4(a) shows the experimentally obtained output characteristics (open squares) at gate voltages of 40, 0 and −40 V of a typical back-gated SL MoS₂ FET with a 300 nm SiO₂ layer as the gate oxide [15]. Figure 4(b) shows the transfer characteristics of the same device in both linear and log-linear plots at a fixed drain bias of 10 mV, the effect of the contact resistance has been de-embedded by using the experimental values [15]. Here we make the assumption that the contact resistance does not change with the gate voltage. The measured room temperature data are chosen for the study here because the contact effects play a less important role at higher temperature. The length and width of the channel are 4 and 9.9 μm respectively. Since the drain voltage is small, the variation of the carrier density and mobility from the source to the drain is ignored. Following the compact model proposed by Jiménez [20], the device characteristics in figure 4 are first modeled by assuming a constant mobility. The calculated currents are shown as solid black lines in figures 4(a) and (b). The carrier statistics are obtained from equations (3)–(5). As can be observed, with constant mobility, the on-state current appears to fit well for high ${{V}_{{\rm gs}}}~\sim ~2040 V.$ However, significant quantitative and more importantly, qualitative discrepancies are observed at low ${{V}_{{\rm gs}}}.$ On the contrary, if we fit the current at low ${{V}_{{\rm gs}}},$ we would see large errors at high ${{V}_{{\rm gs}}}.$ Thus we remodeled the devices characteristics by taking both the carrier statistics, and the ${{V}_{{\rm gs}}}-dependence$ of the electron mobility into account. This calculation is shown as red lines in figures 4(a) and (b). The impurity density is used as the fitting parameter, with value of ∼4 × 10¹² cm⁻². The excellent fit of the ${{V}_{{\rm gs}}}-dependent$ ${{\mu }_{{\rm d}}}$ model to the experimental data over several orders of magnitude change in current indicates that if we use equation (10) or even equation (12) to extract the field-effect mobility from the FET transfer characteristics, we will be in significant error. Both the quantum capacitance and the density-dependent mobility must be included for proper extraction.

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Figures 4(c)–(e) show the calculated room temperature Fermi level in the SL MoS₂ channel, transfer characteristics with constant and ${{V}_{{\rm gs}}}-dependence$ mobilities respectively. The device structure is the same with that in figures 4(a) and (b) and ${{N}_{d}}$ is fixed at 4 × 10¹² cm⁻². In the sub-threshold region, the drain current is dominated by the carrier density increasing with ${{V}_{{\rm gs}}}.$ Thus the threshold voltage ${{V}_{{\rm th}}}$ can be defined as the voltage when the transfer characteristic curve has the highest curvature, as shown by the vertical dashed line in figures 4(c)–(e). ${{V}_{{\rm th}}}$ distinguishes the sub-threshold region and the on-state region that described by equations (6) and (7) respectively. For current structure, ${{V}_{{\rm th}}}$ is ∼−55 V. To further prove the validity of the method of extracting ${{V}_{{\rm th}}},$ we find that when ${{V}_{{\rm gs}}}={{V}_{{\rm th}}},$ ${{E}_{{\rm f}}}$ is located ∼0.66 eV above the midgap, as shown in figure 4(c). This is also the Fermi level when ${{C}_{{\rm q}}}\approx {{C}_{{\rm ox}}},$ as can be observed in figure 1(b). Once the threshold voltage is extracted, one can now estimate the carrier drift mobility in the channel at room temperature with combining the empirical expression proposed in [3] and equation (7) for ${{n}_{{\rm ch}}}{\mkern 1mu} \leqslant$ 10¹³ cm⁻²:

$$\begin{eqnarray}&&\begin{array}{lllllllllllllll} {{\mu }_{{\rm d}}}\approx 3500{{\left( \frac{{{N}_{d}}}{{{10}^{11}}{\rm c}{{{\rm m}}^{-2}}} \right)}^{-1}} \\ \quad \quad \times \left\{ A\left( {{\varepsilon }_{e}} \right)+{{\left[ \frac{1}{q}\frac{{{C}_{{\rm ox}}}{{C}_{{\rm dq}}}\left( {{V}_{{\rm gs}}}-{{V}_{{\rm th}}} \right)}{\left( {{C}_{{\rm ox}}}+{{C}_{{\rm dq}}} \right)\cdot {{10}^{13}}{\rm c}{{{\rm m}}^{-2}}} \right]}^{1.2}} \right\} \\ \quad \quad \times \left( {\rm c}{{{\rm m}}^{2}}\;{{{\rm V}}^{-1}}\;{{{\rm s}}^{-1}} \right), \\ \end{array}\end{eqnarray} \tag{ 13 }$$

where $A\left( {{\varepsilon }_{e}} \right)$ is a fitting constant depending on ${{\varepsilon }_{e}},$ for single-gated MoS₂ FET with SiO₂ gate oxide, $A\left( {{\varepsilon }_{e}} \right)$ is ∼0.036 [3].

To further show the discrepancy between the field-effect mobility and the drift mobility in the device channel, we calculate the transfer characteristics of a SL MoS₂ FET as a function of temperature, using the same parameters as used in figure 4. The example transfer curves at temperatures 4, 100, 200 and 300 K are shown in figure 5(a). Because ${{\mu }_{{\rm FE}}}$ is usually extracted from the measured transfer characteristics in the region that appears to be linear [15], for example, for ${{V}_{{\rm gs}}}~\sim ~2040 V$ in figure 4(b), here we take the carrier mobility at ${{V}_{{\rm gs}}}~\sim ~20 V$ as a case study. The carrier density at ${{V}_{{\rm gs}}}~\sim ~20 V$ is ${{n}_{{\rm ch}}}$ ∼ 5.4 × 10¹² cm⁻². The field-effect mobilities calculated using equation (10) are shown by the red line in figure 5(b). Because of the derivative term in equation (10), ${{\mu }_{{\rm FE}}}$ is proportional to the slope of the tangent to the ${{I}_{{\rm d}}}$–${{V}_{{\rm gs}}}$ curve, as indicated by the red lines in figure 5(a). The black curve in figure 5(b) shows ${{\mu }_{{\rm d}}}$ calculated using our transport model. As we can see from figure 5(b), ${{\mu }_{{\rm FE}}}$ is higher than μ_d over the entire temperature range. Moreover, the error $\Delta \mu$ $\left( ={{\mu }_{{\rm FE}}}-{{\mu }_{{\rm d}}} \right)$ is not constant as the temperature varies. The value of $\Delta \mu$ depends on the dependence of ${{\mu }_{{\rm d}}}$ on ${{V}_{{\rm gs}}},$ as was shown in figure 3(b). The faster ${{\mu }_{{\rm d}}}$ increases with ${{V}_{{\rm gs}}},$ the higher is the discrepancy $\Delta \mu .$ ${{\mu }_{{\rm FE}}}$ calculated by equation (10) shows a much higher value of ∼104 cm² V⁻¹ s⁻¹ at 300 K while ${{\mu }_{{\rm d}}}$ is ∼50 cm² V⁻¹ s⁻¹. Conversely at 4 K, since ${{\mu }_{{\rm d}}}$ starts to saturate at very low $\Delta {{V}_{{\rm gs}}},$ ${{\mu }_{{\rm FE}}}$ (∼190 cm² V⁻¹ s⁻¹) is only slightly higher than ${{\mu }_{{\rm d}}}$ (∼175 cm² V⁻¹ s⁻¹). At temperature lower than 20 K, one can approximate ${{\mu }_{{\rm FE}}}\approx {{\mu }_{{\rm d}}}$ with error less than 10%. Over 20 K, $\Delta \mu$ first increases and then decreases with increasing temperature, leading to an apparent increase of ${{\mu }_{{\rm FE}}}$ at temperatures ranging from ∼30 to ∼80 K. This observation can partially explain the experimentally obtained decrease of the field-effect mobility as the temperature is lowered [9]. Thus we conclude that ${{\mu }_{{\rm FE}}}$ extracted from the device transfer characteristics by equation (10) not only overestimates the electron mobility, but can also show a false temperature dependence. The red line in figure 5(b) shows an anomalous increase of mobility with temperature for 30 K < $T~\lt ~80 K.$ This is not related to any real scattering mechanism, but rather has roots in using incorrect carrier statistics.

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To accurately extract the carrier transport properties from the device measurements, the field-effect mobility may be obtained by:

$$\begin{eqnarray}&&{{\mu }_{{\rm FE}\_{\rm acc}}}=\frac{{{I}_{{\rm d}}}}{{{V}_{{\rm gs}}}-{{V}_{{\rm th}}}}\left[ \frac{L}{W{{\left( C_{{\rm ox}}^{-1}+C_{{\rm dq}}^{-1} \right)}^{-1}}{{V}_{{\rm ds}}}} \right].\end{eqnarray} \tag{ 14 }$$

${{\mu }_{{\rm FE}\_{\rm acc}}}$ extracted from the calculated transfer curves in figure 5(a) using equation (14) are shown as open triangle symbols in figure 5(b) with ${{V}_{{\rm th}}}$ taken as −55 V. We can see a very good agreement between ${{\mu }_{{\rm FE}\_{\rm acc}}}$ and ${{\mu }_{{\rm d}}}.$ Now ${{\mu }_{{\rm FE}\_{\rm acc}}}$ is proportional to the slope of the straight line joining ${{I}_{{\rm d}}}\left( {{V}_{{\rm th}}} \right)$ to ${{I}_{{\rm d}}}\left( {{V}_{{\rm gs}}}=20\;V \right),$ as indicated in figure 5(a) by blue dashed lines. Comparing the slopes of the blue and red lines in figure 5(a), one can easily see the error induced by equation (10). Note that the estimation performed here should be used under the assumption of perfect Ohmic contact (or after contact resistance has been effectively eliminated). For current TMD semiconductors, it is still a challenge to obtain Ohmic contacts with high transparency. TMD FETs with the same channel material but with different contact metals can show very different electrostatic characteristics, and thus will give false information of the channel carrier statistics and mobillities [21–23]. A number of efforts have been made to improve the contact [16, 24–28], and remarkable low contact resistances have been achieved [29–31].

In conclusion, we have investigated the importance of the carrier statistics and quantum capacitance in understanding the characteristics of 2D crystal semiconductor electronic devices. The commonly used expressions for extracting the carrier density and field-effect mobility from the transfer characteristics of 2D semiconductor FET are demonstrated to be only valid for very limiting conditions, and prone to severe errors. By combining the correct carrier statistics, quantum capacitance, and density-dependent mobitlities, we prescribe a new method to extract the correct mobilities from the FET measurements. The results presented here are expected to be useful to place our understanding of the fundamental properties of 2D crystal semiconductors on a more firm foundation.

Acknowledgments