Protecting quantum memories using coherent parity check codes

Before beginning our presentation of the CPC framework, we briefly outline the key concepts and shortcomings of conventional stabiliser QEC codes. This will provide a point-of-reference with which to compare CPC codes.

The circuit in figure 1 shows the basic structure of a traditional stabiliser code. A register of data qubits, ${| \psi \rangle }_{D}$, is entangled with a number of blank redundancy qubits, ${| 0\rangle }_{R}$, via an encoding operation to create a logical qubit ${| \psi \rangle }_{L}$. At this stage, the data previously stored solely in ${| \psi \rangle }_{D}$ is distributed across the combined Hilbert space of data and redundancy qubits [22].

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Once the quantum information has been encoded as a logical qubit, errors can be detected by making parity measurements. In practice, this is achieved via the construction shown to the right of the circuit in figure 1. A parity check ${ \mathcal P }$ is applied to the logical qubit, and the result copied to an auxillary qubit A, which is prepared in the conjugate basis by Hadamard gates H. Note that a parity check ${ \mathcal P }$ is a product of Pauli operators and has eigenvalues ±1 (for the definition of the Pauli group, consult appendix A). The auxillary qubit is then measured to yield a syndrome. For a well chosen parity check, this syndrome measurement provides information about whether the logical qubit has been subject to an error.

It has been shown that QEC codes based on the above construction can achieve arbitrarily low logical error rates, provided certain threshold conditions are met by qubits at the physical level [23]. However, constructing efficient codes with this approach is difficult owing to limitations on the type of parity check that can implemented. In order to ensure that the syndrome measurement of qubit A does not decohere the encoded quantum information, the parity check must stabilise the logical qubit. Formally [24], we can write this requirement as follows

$$\begin{eqnarray}&&{ \mathcal P }\in { \mathcal S },\end{eqnarray} \tag{ 1 }$$

where the stabiliser ${ \mathcal S }=\langle {K}_{i},\,\ldots ,\,{K}_{n}\rangle$ is a sub-group of the Pauli group ${ \mathcal G }$ defined by

$$\begin{eqnarray}&&{ \mathcal S }=\{{K}_{i}\ | \ {K}_{i}{| \psi \rangle }_{L}=(+1){| \psi \rangle }_{L},[{K}_{i},{K}_{j}]=0,{K}_{i}\ne -{\mathbb{1}},\forall \ (i,j)\}\in { \mathcal G },\end{eqnarray} \tag{ 2 }$$

where K_{{i, j}} are the elements of the stabiliser group and ${| \psi \rangle }_{L}$ is the logical codeword. The challenges of constructing traditional stabiliser quantum codes are therefore twofold. First, an appropriate encoding operation must be built to create the logical qubit. Second, a compatible set of stabiliser parity checks needs to be discovered so that errors can be checked without compromising the encoded quantum data. As a result of these challenges, the majority of existing QEC codes are limited to the simplest case in which only a single qubit is encoded per logical block. Such [[n, 1, d]] codes can be considered quantum analogues of the most basic classical repetition codes, and incur high overheads in terms of the number of redundancy qubits necessary to achieve the desired error suppression rate.

The fundamental CPC gadget, shown in figure 2, is the building block upon which all CPC codes are based [3]. The basic premise behind the CPC gadget is that the parity of the quantum register is never explicitly measured. Instead, parity information is stored coherently as quantum data and compared over time. This is made possible by the gadget's symmetric encode-error-decode structure.

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The CPC gadget takes a multi-qubit register ${| \psi \rangle }_{D}$ and a parity qubit p, prepared in the state ${| 0\rangle }_{p}$, as its input. The action of the encode stage of the gadget, labelled U_enc in figure 2, is to apply the parity operator ${ \mathcal P }$ to the register and record the outcome in parity qubit p. Rather than measuring the syndrome immediately, the parity qubit is kept coherent during a wait stage in which the register is potentially subject to an error E. Note that we are not yet considering errors that occur on the parity qubit. In section 2.5, we outline how multiple CPC gadgets can be combined to allow for error detection on the combined system of register and parity qubits.

Following the wait stage, the parity qubit is disentangled from the register via a decoder operation, labelled U_dec in figure 2, which is the unitary inverse of the encoder. The encoder applies the parity operator ${ \mathcal P }$ to the register and the decoder applies its inverse ${{ \mathcal P }}^{\dagger }$. The final syndrome measurement of parity qubit p tells us whether the results of these two parity checks differ. For an appropriately chosen parity check, this syndrome information can indicate whether an error occurred during the wait stage.

To prove its error detection capabilities, it is convenient to rearrange the circuit for the CPC gadget into the form shown in figure 3. This rewrite is achieved by moving the error operator E through the parity check operator ${ \mathcal P }$. Both the error gate and the parity check gate are Pauli group operations. A property of the Pauli group is that its elements either commute or anti-commute with one another. Consequently, the effect of pushing the error operator to the front of the circuit is to introduce a global phase ${\rm{\Phi }}(E,{ \mathcal P })$ on the register which is controlled by the parity qubit. This global phase is dependent upon both the parity check and the error operator, and is defined as follows,

$$\begin{eqnarray}{\rm{\Phi }}(E,{ \mathcal P })=\left\{\begin{array}{ll}(+1){{\mathbb{1}}}_{D}, & \mathrm{if}\ [E,{ \mathcal P }]=0\\ (-1){{\mathbb{1}}}_{D}, & \mathrm{if}\ [E,{ \mathcal P }]\ne 0,\end{array}\right.\end{eqnarray} \tag{ 3 }$$

where ${{\mathbb{1}}}_{D}$ is the identity operator on the data register and the commutator is given by $[E,{ \mathcal P }]=E\,\bullet \,{ \mathcal P }-{ \mathcal P }\,\bullet \,E$. Note that, after the rewrite, the controlled parity check operators are adjacent to each other and cancel. The full mathematical action of the CPC circuit U_CPC, can now be expressed as follows,

$$\begin{eqnarray}&&{U}_{\mathrm{CPC}}{| \psi \rangle }_{D}{| 0\rangle }_{p}=({\mathbb{1}}+{\rm{\Phi }}(E,{ \mathcal P }))E{| \psi \rangle }_{D}{| 0\rangle }_{p}+({\mathbb{1}}-{\rm{\Phi }}(E,{ \mathcal P }))E{| \psi \rangle }_{D}{| 1\rangle }_{p}.\end{eqnarray} \tag{ 4 }$$

Using the definition of the global phase operator ${\rm{\Phi }}(E,{ \mathcal P })$ given in equation (3), the output of the CPC gadget simplifies to

$$\begin{eqnarray}{U}_{\mathrm{CPC}}{| \psi \rangle }_{D}{| 0\rangle }_{p}=\left\{\begin{array}{ll}E{| \psi \rangle }_{D}{| 0\rangle }_{p}, & \mathrm{if}\ [E,{ \mathcal P }]=0\\ E{| \psi \rangle }_{D}{| 1\rangle }_{p}, & \mathrm{if}\ [E,{ \mathcal P }]\ne 0.\end{array}\right.\end{eqnarray} \tag{ 5 }$$

From the above we can see that eventual syndrome measurement of parity qubit p depends only upon whether ${ \mathcal P }$ commutes with E. If no error occurs during the wait stage, then $E={{\mathbb{1}}}_{D}$ and the syndrome is measured deterministically as '0'. Likewise, if an error does occur, but it commutes with the parity operator, $[E,{ \mathcal P }]=0$, then the syndrome is also '0'. Finally, if the error anti-commutes with the parity check, $[E,P]\ne 0$, then the syndrome is measured as '1'. A quantum error detection protocol can therefore be constructed from the CPC gadget by selecting a parity check that anti-commutes with the error to be identified. In the following subsections, we will show that CPC gadgets can be combined to create full QEC codes which can detect and localise multiple error types simultaneously.

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The CPC gadget can be thought of as an extended measurement of the $\pm {{\mathbb{1}}}_{D}$ operator on the data register, where the sign depends upon the commutation relation between ${ \mathcal P }$ and E. As the $\pm {{\mathbb{1}}}_{D}$ operator is trivially non-disturbing for all quantum states, there is no need for CPC codes to encode quantum information as logical qubits. Furthermore, it is clear from the output of the CPC gadget in equation (5), that the quantum data register is completely disentangled from the parity qubit prior to syndrome measurement. As a result, the only requirement on the parity checks is that they are Pauli group operators

$$\begin{eqnarray}&&{ \mathcal P }\in { \mathcal G }.\end{eqnarray} \tag{ 6 }$$

Recall from equation (1), that for traditional codes, the choice of parity checks is limited to the set of stabilisers of the encoded logical qubits. The CPC framework lifts this restriction.

It should be noted that, as the encoders and decoders consists entirely of Clifford operations, CPC codes form a class of stabiliser codes. A detailed explanation of the correspondence between CPC codes and stabiliser codes can be found in Chancellor et al [3]. The specific strength of the CPC framework lies in the fact that the symmetric encode-error-decode structure provides a general method for creating a stabiliser code using any sequence of parity checks.

We now provide specific examples of CPC gadgets to detect bit flips and phase flips on a two-qubit data register $| {\psi }_{{AB}}\rangle$. Following this, we describe how the two types of CPC gadget can be combined to create a [[4, 2, 2]] detection code.

In order to design a CPC gadget that will detect single bit flips on the register $| {\psi }_{{AB}}\rangle$, we need a parity check that anti-commutes with the errors in the set ${{ \mathcal E }}_{X}=\{{X}_{A},{X}_{B}\}$. Setting ${{ \mathcal P }}_{{AB}}={Z}_{A}{Z}_{B}$ satisfies this requirement to give the bit-flip CPC gadget depicted in figure 4. Note that X and Z are Pauli operators which are defined in appendix A. It is useful to rewrite the circuit in figure 4 in terms of ${\rm{CNOT}}$ gates using the gate substitution defined by the following matrix equation

$$\begin{eqnarray}&&{{\rm{CZ}}}_{{q}_{2}}^{{q}_{1}}=({{\mathbb{1}}}_{{q}_{1}}\otimes {H}_{{q}_{2}})\,\bullet \,{{\rm{CNOT}}}_{{q}_{2}}^{{q}_{1}}\,\bullet \,({{\mathbb{1}}}_{{q}_{1}}\otimes {H}_{{q}_{2}}),\end{eqnarray} \tag{ 7 }$$

where ${\rm{CZ}}$ is a controlled-Z gate and q₁ and q₂ are the input qubits. The resultant circuit is shown in figure 5. In this form, the operation of the CPC gadget can easily be visualised by considering the propagation of errors through the decoder. A ${\rm{CNOT}}$ gate will propagate a bit-flip error from the control qubit q₁ to the target q₂ as follows,

$$\begin{eqnarray}&&{{\rm{CNOT}}}_{{q}_{2}}^{{q}_{1}}\,\bullet \,({X}_{{q}_{1}}\otimes {{\mathbb{1}}}_{{q}_{2}})\,\bullet \,{{\rm{CNOT}}}_{{q}_{2}}^{{q}_{1}}={X}_{{q}_{1}}\otimes {X}_{{q}_{2}}.\end{eqnarray} \tag{ 8 }$$

Implementing the above propagation rule, the red and blue arrows in figure 5 depict the possible detection pathways for bit-errors from the wait stage to the parity check qubit.

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A CPC gadget that detects errors from the set ${{ \mathcal E }}_{Z}=\{{Z}_{A},{Z}_{B}\}$ can be obtained using a parity check of the form ${{ \mathcal P }}_{{AB}}={X}_{A}{X}_{B}$. Figure 6 depicts the phase-flip CPC gadget expressed in terms of the conjugate-propagator gate ${{\rm{\Lambda }}}_{{q}_{2}}^{{q}_{1}}$ given by

$$\begin{eqnarray}&&{{\rm{\Lambda }}}_{{q}_{2}}^{{q}_{1}}=({{\mathbb{1}}}_{{q}_{1}}\otimes {H}_{{q}_{2}})\,\bullet \,{{\rm{CNOT}}}_{{q}_{1}}^{{q}_{2}}\,\bullet \,({{\mathbb{1}}}_{{q}_{1}}\otimes {H}_{{q}_{2}}).\end{eqnarray} \tag{ 9 }$$

The conjugate-propagator gate is a symmetric two-qubit operator with the following propagation rule for Z errors

$$\begin{eqnarray}&&{{\rm{\Lambda }}}_{{q}_{2}}^{{q}_{1}}\,\bullet \,({Z}_{{q}_{1}}\otimes {{\mathbb{1}}}_{{q}_{2}})\,\bullet \,{{\rm{\Lambda }}}_{{q}_{2}}^{{q}_{1}}\to {Z}_{{q}_{1}}\otimes {X}_{{q}_{2}}.\end{eqnarray} \tag{ 10 }$$

Phase-flip errors in the wait stage are copied to the parity qubit via a conjugate-propagator gate which converts the Z error to an X error that can be detected in the computational basis. Figure 6 depicts the possible error propagation pathways for errors in the phase-flip CPC gadget.

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We now show how the bit-flip and phase-flip CPC gadgets can be combined to form a full quantum error detection code. Figure 7 shows the CPC circuit formed by combining the bit-flip gadget with the phase-flip gadget. By considering the error propagation rules outlined in the previous subsections, it can be verified that this circuit will detect errors which occur on the register qubits $| {\psi }_{{AB}}\rangle$, but not errors which occur the parity qubits p₁ and p₂. We now show how the code can be modified to enable error detection across all four of the qubits.

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The blue arrows in figure 7 show that a phase-flip error on the first parity qubit p₁ will propagate errors to the register in an undetectable way. Fortunately, a detection pathway can be created by applying a conjugate-propagator gate between the parity qubits at the end of the decoder (from now on, we will refer to these additional gates as 'cross-checks'). As shown by the orange arrows in figure 8, this cross-check propagates the phase-error to the parity check qubit p₂ and converts it to an X error that can be picked up by a computational basis measurement. With the addition of the cross-check, the circuit becomes a fully functional [[4, 2, 2]] quantum error detection code. The single-qubit error syndromes are given in table 1, and demonstrate the code can detect the occurrence of X, Y and Z errors on any of the 4 qubits.

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Table 1.  The syndrome table for the [[4, 2, 2]] quantum error detection code. If no errors occur, the code returns a '00' syndrome. If a single X, Y or Z error occurs on any of the four qubits, a non-zero syndrome is returned.

Error	Syndrome
I	${0}_{{p}_{1}}{0}_{{p}_{2}}$
${X}_{A},{X}_{B},{X}_{{p}_{1}},{Z}_{{p}_{2}}$	${1}_{{p}_{1}}{0}_{{p}_{2}}$
${Z}_{A},{Z}_{B},{Z}_{{p}_{1}},{X}_{{p}_{2}}$	${0}_{{p}_{1}}{1}_{{p}_{2}}$
${Y}_{A},{Y}_{B},{Y}_{{p}_{1}},{Y}_{{p}_{2}}$	${1}_{{p}_{1}}{1}_{{p}_{2}}$

As the [[4, 2, 2]] code is a detection code, the syndromes do not give us enough information to pinpoint which qubit the error occurred on. The construction of full error correcting CPC codes, that can both identify and localise errors, will be outlined in the next section.

The [[4, 2, 2]] quantum error detection code illustrates the basic principles behind the operation of a CPC code. The encoder is constructed by combining a bit-flip CPC gadget with a phase-flip CPC gadget. Under this canonical ordering, errors on the parity qubits are identifiable via the addition of the cross-check operators. A compact way of representing CPC codes is in terms of adjacency matrices which describe the connectivity between the register and parity qubits. For example, the adjacency matrices for the [[4, 2, 2]] code are

where m_b represents the bit-checks, m_p the phase-checks and m_c the cross-checks. For the bit-flip and phase-flip adjacency matrices, m_b and m_p, the rows refer to the data qubits and the columns the parity qubits. Looking at the bit-flip matrix, we can see that both register qubits connect to parity qubit p₁ via ${\rm{CNOT}}$ gates in accordance with the circuit in figure 8. Likewise, matrix m_P tells us that both register qubits are connected to parity qubit p₂ via conjugate-propagator gates. Finally, from matrix m_c, we see that there is a single cross-check between parity qubits p₁ and p₂. The cross-checks result in a matrix that is always symmetric. We follow [3] in representing this as an upper triangular matrix, so that the number of non-zero entries corresponds to the number of two-qubit gates.

We are now in a position to extend the CPC framework to enable the description of more general codes. The canonical form of an [[n, k, d]] CPC code is shown in figure 9. Such codes have k data qubits, ${| \psi \rangle }_{D}=| {\psi }_{{D}_{1}}{\psi }_{{D}_{2}}...{\psi }_{{D}_{k}}\rangle$, and m = n − k parity qubits, ${| 0\rangle }_{P}=| {0}_{{p}_{1}}{0}_{{p}_{2}}...{0}_{{p}_{m}}\rangle$. As with the detection schemes described previously, the encode stage of a general CPC code involves successive rounds of cross-checks, bit-checks and then phase-checks. The sequence of gates within each stage of the encoder can be compactly described in terms of adjacency matrices of the form

where b_xy, h_xy, c_xy are binary values. As mentioned previously, for simplicity, the cross-check matrix m_c is always represented as an upper triangular matrix.

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We have now outlined the canonical structure of CPC codes, and shown how they can be represented in terms of three adjacency matrices. The CPC framework removes the need to start out by redundantly encoding quantum data, and allows QEC protocols to be implemented with any parity check. As such, the CPC framework essentially reduces the task of deriving QEC codes to a classical decoding problem.

A new [[n, k, d = ?]] CPC circuit can be generated simply by selecting a random instance of the adjacency matrices for an n-qubit code with k data qubits. The symmetric encode-error-decode structure of the CPC code will ensure that the random sequence of parity checks this set of adjacency matrices represents does not decohere the register. The only task necessary to verify whether the circuit represents a working CPC code is to measure the code distance d. This can be done by testing the circuits with all of the errors in the chosen error model. If each error produces a unique syndrome, then the code distance is d ≥ 3, and the circuit represents a working CPC code.

In this paper we only consider quantum memories. As a result, the codes under consideration are Clifford circuits. The code distance can therefore be efficiently verified for small-distance codes using a stabiliser simulator such as [25, 26]. Alternatively, we have developed an algorithm specifically for calculating the syndromes of CPC codes, which is based on error propagation rules outlined in sections 2.3 and 2.4. This algorithm is described in appendix C, and can be implemented in less than 200 lines of Python code.

Our experiment on the IBM 5Q encodes a single input state $| {\psi }_{{AB}}\rangle =| {+}_{A}{0}_{B}\rangle$ using a [[4, 2, 2]] CPC quantum memory of the type described in section 2.5. The $| {+}_{A}{0}_{B}\rangle$ state is an easy-to-prepare quantum state that is susceptible to both bit- and phase-flip errors, and therefore provides a suitable test of the [[4, 2, 2]] CPC code as a quantum memory.

Ultimately, the condition for success for a quantum code is to test whether the encoded protocol has a lower logical error rate than the equivalent circuit before encoding. In the case of quantum memory, the circuit that is encoded is simply an extended identity operation. The usefulness of the [[4, 2, 2]] code could therefore be assessed by comparing the fidelity of the encoded output to the equivalent output of an unprotected two-qubit data register. However, the gate-error rates on the IBM 5Q hardware are too high for such a comparison to yield a positive result. This problem is compounded by the fact that the IBM hardware limits the experiment to a single encode–decode cycle, meaning certain regions of the [[4, 2, 2]] circuit—before the encoder and after the decoder—are left unprotected. Consequently, the aim of the experiment presented here is restricted to demonstrating that, whilst not suppressing the logical error rate, the [[4, 2, 2]] CPC code does detect errors. We now describe the method by which this is achieved.

The compiled [[4, 2, 2]] CPC code is run multiple times with the input state $| {\psi }_{{AB}}\rangle =| {+}_{A}{0}_{B}\rangle$ on the IBM 5Q hardware. At the end of each CPC code cycle, the parity qubits are measured to provide a syndrome designed to indicate if an error has occurred. An approximation to the output state of the register is reconstructed from the experimental data using quantum state tomography. The quality of this output is quantified by calculating its fidelity relative to the input state $| {+}_{A}{0}_{B}\rangle$. In this experiment we compare the output fidelity of the [[4, 2, 2]] protocol before and after post-selection. In the former, the syndrome information is ignored, whereas in the latter it is used to determine which experimental runs are discarded during post-selection. The condition for success is that the post-selection should improve the output fidelity. If this is the case, it will demonstrate that the [[4, 2, 2]] CPC code is detecting errors and produces useful syndrome information.

Our experiment is run on the IBMQX4 version of the IBM 5Q, the technical details for which can be found in [29]. Figure 10 depicts the 'bow tie' layout of the chip. The arrows represent the allowed ${\rm{CNOT}}$ operations between qubits. The direction of the arrow indicates the preferred ${\rm{CNOT}}$ direction, but the operation can be reversed via the circuit transformation shown in figure 11(a).

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The [[4, 2, 2]] code, as depicted in figure 8, has two data qubits {A, B} and two parity qubits {p₁, p₂}. In this experiment, the code qubits are mapped onto the physical qubits of the IBMQX4 device as follows: $\{A\to {Q}_{3},B\to {Q}_{0},{p}_{1}\to {Q}_{2},{p}_{2}\to {Q}_{1}\}$. The input state becomes $| {\psi }_{{AB}}\rangle ={| +\rangle }_{{Q}_{3}}\otimes {| 0\rangle }_{{Q}_{0}}$, and the resultant circuit is shown in figure 12(a). The two conjugate-propagator gates marked in red are not possible on the IBMQX4, as there is no connectivity between qubits Q₃ and Q₁ (see figure 10). The [[4, 2, 2]] CPC circuit must therefore be modified to accommodate this hardware constraint.

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The first step in compiling the [[4, 2, 2]] circuit for the IBMQX4 is to rearrange the gates into the order shown in figure 12(b). This is a departure from the canonical form of CPC codes outlined in section 2.6. However, it can easily be checked that the modified circuit remains a functional [[4, 2, 2]] CPC code capable of detecting single X and Z errors on any of the qubits during the wait-stage.

In the rearranged form of the circuit in figure 12(b), and when the input state is $| {\psi }_{{AB}}\rangle ={| +\rangle }_{{Q}_{3}}\otimes {| 0\rangle }_{{Q}_{0}}$, it can be seen that the action of the gates highlighted in green is the identity. The green gates can therefore be omitted from the circuit without affecting the function of the quantum memory. Following this simplification, the only operation that remains prohibited by the IMBQX4's connectivity constraints is the red conjugate-propagator gate between Q₁ and Q₃ in the decoder. One way of resolving this problem is to perform a ${\rm{SWAP}}$ operation between Q₂ and Q₁, as shown in figure 12(c). The ${\rm{SWAP}}$ gate exchanges the positions of the p₁ and p₂ parity check qubits, enabling the red conjugate-propagator gate to be performed via a nearest-neighbour interaction. A ${\rm{SWAP}}$ gate is achieved via the application of three ${\rm{CNOT}}$ gates (see figure 11(c)), and is therefore an expensive operation that should be used sparingly. In section 6, we explore how the CPC code design process can be used to minimise the ${\rm{SWAP}}$ gate count when compiling larger codes onto quantum hardware.

So far, we have considered a simplified model of CPC code operation in which it is assumed errors only occur during the wait-stage between the encoder and the decoder. However, we have observed that the error rates for ${\rm{CNOT}}$ operations and readout on the IBMQX4 are of the order 10⁻² (daily calibration data can be obtained from the IBM Q website [2]). This realistically means that any quantum code must be designed to detect errors that occur at any point in the circuit. To this end, figure 12(d) shows the IMBQX4-compiled [[4, 2, 2]] circuit under a more general error model.

Fault tolerant circuit construction ordinarily necessitates the introduction of additional qubits [30–32]. However, in this particular instance of the [[4, 2, 2]] CPC code with a known ${| +\rangle }_{{Q}_{3}}\otimes {| 0\rangle }_{{Q}_{0}}$ input, it can be verified that a single fault at any of the locations marked on figure 12(d) will not propagate a multi-qubit error to the register without triggering a syndrome. The circuit can therefore be considered to have been hardened against single-qubit errors in the encode and decode stages of the circuit. It should be noted, however, that this does not extend the circuit to full fault tolerance when implemented on the IBMQX4 chip. State preparation and measurement errors are not accounted for, nor is the [[4, 2, 2]] code capable of detecting correlated two-qubit errors that might occur after a ${\rm{CNOT}}$ gate. Another issue is that the circuit allows certain single-qubit errors to propagate to the register in an undetectable way. It is not currently possible to measure, then reset a qubit on the IBMQX4 via the public API. As a result, our implementation is restricted to a single encode–decode cycle, meaning the undetected single-qubit errors will reduce the output fidelity. However, as outlined in [3], CPC codes can be expressed in terms of stabiliser codes. Adopting this approach allows CPC codes to be implemented using existing syndrome extraction techniques, and enables errors to be decoded over multiple cycles. Assuming access to hardware that allows qubit reset, CPC codes implemented in this way would be tolerant of the single-qubit errors that propagate to the register.

The IBM Quantum Information Software Kit (QISKIT) [33] was used to prepare the [[4, 2, 2]] experiment for quantum state tomography on the output qubits Q₀ and Q₃. QISKIT quantum tomography tools were used to create a set of nine circuits from the original [[4, 2, 2]] circuit (depicted in figure 12(c)), each of which was designed to measure the output qubits Q₀ and Q₃ in a different measurement basis from the list {XX, XY, XZ, YX, YY, YZ, ZX, ZY, ZZ}. These quantum tomography circuits were then run multiple times to create a distribution of results that could be used reconstruct an approximation to the density matrix of the output state. The QISKIT method used for state reconstruction from the experimental data was the fast maximum likelihood method for quantum tomography, a description of which can be found in [34].

The quantum tomography circuits for the [[4, 2, 2]] memory were run in batches of 8192 shots. After each batch, the QISKIT maximum likelihood method was used to reconstruct the density matrix ρ_dd of the directly-decoded output before post-selection. The syndrome qubits were then inspected to determine which of the shots in the batch should be discarded during post-selection. State reconstruction was then performed again on the reduced set to obtain a post-selected density matrix ρ_ps. The quality of the directly-decoded and post-selected output state for each batch was quantified by calculating the fidelity, $F(\rho )={(\mathrm{Tr}[\sqrt{{\rho }^{1/2}\sigma {\rho }^{1/2}}])}^{2}$, where σ is the target density matrix. For the chosen input state $| {\psi }_{{AB}}\rangle ={| +\rangle }_{{Q}_{3}}\otimes {| 0\rangle }_{{Q}_{0}}$, the target density matrix is given by

$$\begin{eqnarray}\sigma =\left(\begin{array}{cccc}\tfrac{1}{2} & 0 & \tfrac{1}{2} & 0\\ 0 & 0 & 0 & 0\\ \tfrac{1}{2} & 0 & \tfrac{1}{2} & 0\\ 0 & 0 & 0 & 0\end{array}\right).\end{eqnarray} \tag{ 13 }$$

The purity of the density matrices, defined by $P(\rho )=\mathrm{Tr}[{\rho }^{2}]$, was also calculated to provide a coherence measure for the output states.

The [[4, 2, 2]] CPC quantum memory circuit, depicted in figure 12(c), was run on the IBMQX4 device between the 25th and 27th November 2017. A summary of the experimental results for state purity, fidelity and yield can be found in table 2. Error bars were calculated as one standard deviation of a single run value consisting of 8192 experimental executions of the quantum tomography circuit set. The standard error of the mean over all 154 runs was too small to be visible on our plots. Calibration data for the device on each of the three days of the experiment can be found in appendix D.

Table 2.  Quality metrics for the reconstructed density matrices before and after post-selection. The fidelity is calculated relative to the target density matrix σ which is defined in equation (13). The yield is the proportion of shots per batch that are retained during the post-selection process. The errors are calculated as one standard deviation of a single run value consisting of 8192 experimental shots.

	Purity, $P(\rho )$	Fidelity, F(ρ)	Yield
Before post-selection, ${\bar{\rho }}_{{dd}}$	0.52 ± 0.02	0.62 ± 0.03	100%
After post-selection, ${\bar{\rho }}_{{ps}}$	0.74 ± 0.03	0.75 ± 0.04	(54 ± 2)%
no. runs: 154 batches of 8192 shots

A total of 154 batches of 8192 shots were run over the course of the experiment. Figure 13 shows a plot of the real components of the elements of ${\bar{\rho }}_{{dd}}$ and ${\bar{\rho }}_{{ps}}$ averaged across the 154 batches. It is immediately clear that the post-selected density matrix ${\bar{\rho }}_{{ps}}$ better preserves the four target elements, which we identify as the non-zero elements in the target state σ given by equation (13). The bar-chart in figure 14 shows these target elements in isolation, from which it is apparent that post-selection has the biggest impact in preserving the strength of the off-diagonal coherences. This can also be seen when comparing the purity values, shown in table 2, for ${\bar{\rho }}_{{dd}}$ and ${\bar{\rho }}_{{ps}}$. The directly-decoded density matrix ${\bar{\rho }}_{{dd}}$ has a purity of $P({\bar{\rho }}_{{dd}})=0.52\pm 0.02$, implying it represents a near-fully mixed classical ensemble with a purity of 0.5. In contrast, the post-selected density matrix ${\bar{\rho }}_{{ps}}$ has a purity of $P({\bar{\rho }}_{{ps}})=0.74\pm 0.03$, suggesting it has undergone only partial decoherence.

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The fidelities of ${\bar{\rho }}_{{dd}}$ and ${\bar{\rho }}_{{ps}}$ relative to the target state are $F({\bar{\rho }}_{{dd}})=0.62\pm 0.03$ and $F({\bar{\rho }}_{{ps}})=0.75\pm 0.04$ respectively. The fidelity of the post-selected state is therefore greater than the directly-decoded state with a confidence level of three standard deviations. From this we can conclude that the [[4, 2, 2]] quantum memory produces useful syndrome information for protecting a $| {\psi }_{{AB}}\rangle =| {+}_{A}{0}_{B}\rangle$ state. A consideration, however, is that the average yield (the proportion of results retained after post-selection) was (54 ± 2)% averaged over the 154 batches.

The results of our experiment with the IBMQX4 device show that the syndrome information produced by a [[4, 2, 2]] CPC quantum memory can be used to improve the fidelity and purity of the code output. The [[4, 2, 2]] CPC code is one the simplest quantum memories, and as such, it was possible to compile the circuit for the IBMQX4 device by inspection. In the following sections, we outline a CPC design process that provides automated methods for compiling and optimising more complex CPC codes onto quantum hardware. As an example, we demonstrate the utility of the CPC design process in the compilation of a custom quantum memory for an idealised seven-qubit ion trap device.

Here we show that the [[4, 2, 2]] CPC detection code, introduced in section 2.5, can be efficiently compiled with an ion trap native gate. For the purposes of this example, we adopt an ion trap with a SP native gate as introduced in equation (15) in section 4. The SP native gate can be transformed into a ${\rm{CNOT}}$ via the application of local unitary operations to its inputs and outputs. A possible mapping, in matrix equation form, is given by

$$\begin{eqnarray}&&{{\rm{CNOT}}}_{{q}_{2}}^{{q}_{1}}=({I}_{{q}_{1}}\otimes {H}_{{q}_{2}})\,\bullet \,({P}_{{q}_{1}}\otimes {P}_{{q}_{2}})\,\bullet \,{F}_{{q}_{2}}^{{q}_{1}}\,\bullet \,({I}_{{q}_{1}}\otimes {H}_{{q}_{2}}),\end{eqnarray} \tag{ 16 }$$

where ${F}_{{q}_{2}}^{{q}_{1}}$ is the matrix representation of the SP gate defined in equation (14), and P is a phase gate defined as $P=\mathrm{diag}(1,-{\rm{i}})$. Realising a ${\rm{CNOT}}$ gate on ion trap hardware, via the above mapping, requires the application of the native gate combined with four single-qubit gates, as shown in figure 15(a). Likewise, figure 15(b) shows how the conjugate-propagator gate can be constructed from the native gate via the addition of six single-qubit operations. We will see that, when the native gates are compiled into a CPC circuit, constructive simplifications become possible to reduce the total number of single-qubit gates required.

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Figure 16 illustrates the steps involved in the compilation and simplification of the [[4, 2, 2]] CPC code with the SP native gate. The un-compiled circuit, expressed in terms of ${\rm{CNOT}}$ and conjugate-propagator gates, is shown in figure 16(a). The first step of compilation involves substituting the ${\rm{CNOT}}$ and conjugate-propagator gates with the SP native interaction, via the circuit rewrites rules defined in figure 15. The resultant circuit is shown in figure 16(b).

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Now that the circuit is written in terms of the native gate, circuit simplifications can be applied to reduce the single-qubit gate count. In figure 16(b), pairs of H gates that cancel to the identity are labelled in red. In the encoder, the H gates labelled in blue are paired with their counterparts from the decoder. We can now exploit the symmetry of the CPC code to further reduce the gate count. The effect of the blue H gates around the wait-stage is to transform X errors into Z errors and vice versa, as described by the following matrix transformations

$$\begin{eqnarray}&&H\,\bullet \,(E=X)\,\bullet \,H=H\,\bullet \,X\,\bullet \,H=Z,\\ &&H\,\bullet \,(E=Z)\,\bullet \,H=H\,\bullet \,Z\,\bullet \,H=X,\end{eqnarray} \tag{ 17 }$$

where E represents the error that occurs in the wait stage. The [[4, 2, 2]] code can detect both X and Z errors, as shown in syndrome table 1 in section 2.5. As a result, the blue H gates do not change the errors into a form that cannot be detected. The blue H gates can therefore be discarded without affecting the operation of the [[4, 2, 2]] code.

Figure 16(c) shows the compiled [[4, 2, 2]] code following the removal of the unnecessary H gates. Notice that both the P gate and the SP gate are described by diagonal matrices in the computational basis. As a result, we have the freedom to move P gates through the SP native gate as shown in figure 15(c). Two P gates combine to form a Z gate as follows $P\,\bullet \,P=Z$. In the circuit in figure 16(c), pairs of P gates are highlighted in red. As Z gates are diagonal in the computational basis, they can also be moved through the SP gates.

In the circuit in figure 16(d), the Z gates and blue P gates have been pushed to the centre of the circuit. In the event that no error occurs, these P gates combine to form a Z error via the relation $Z=P\,\bullet \,P$. However, the locations of these errors are known, and they can therefore be accounted for in post-processing. If an error does occur, the effect of symmetric P gates about the wait stage, E, is to transform X errors into Y errors and vice versa, as described by the following matrix transformation rules

$$\begin{eqnarray}&&P\,\bullet \,(E=X)\,\bullet \,P=P\,\bullet \,X\,\bullet \,P=(-{\rm{i}})Y,\\ &&P\,\bullet \,(E=Y)\,\bullet \,P=P\,\bullet \,Y\,\bullet \,P=(-{\rm{i}})X,\end{eqnarray} \tag{ 18 }$$

where the (−i) global phase does not affect the syndrome measurement. These transformations are unproblematic as the [[4, 2, 2]] code can detect both X and Y errors (see syndrome table 1). As the effect of the blue P gates can be described in terms of single-qubit Clifford operations on the output, they can be removed from the circuit and accounted for in post-processing. There are also P gates highlighted in green, located on the register qubits at the beginning and end of each error cycle. These gates occur before the first round of CPC checks, and can therefore be removed from the circuit without affecting the final syndrome readout. Finally, the Z gates located symmetrically about the wait-stage introduce a global phase to the errors. This global phase does not affect the propagation of errors through the circuit, meaning the Z gates can be removed. It should be noted that the above simplifications will result in a modified syndrome table. However, the no-error case will remain unique meaning the function of the code is maintained.

The final simplified form of [[4, 2, 2]] CPC code compiled with the SP native gate is shown in figure 16(e). The single-qubit gate count in the encoder has been lowered from 26 gates in the original compiled circuit (figure 16(b)), to 4 gates in final circuit (figure 16(e)).

We have now shown that the [[4, 2, 2]] code can be efficiently compiled with the SP native gate. Most of the single-qubit corrections can be eliminated, either by direct cancellation between adjacent Hadamards, or by moving P gates through the circuit. We now show that efficient CPC code translation, from the idealised ${\rm{CNOT}}$ version to the hardware-compiled version, is possible for a range of native gate types. We begin by outlining the general requirements for two-qubit gates in a CPC circuit.

In a CPC code, the role of two-qubit interaction gates is to distribute error information from the register to the parity qubits. For example, ${\rm{CNOT}}$ gates propagate bit-errors from their control to target via the rule in equation (8). More generally, we require that the two-qubit CPC gate, ${{\rm{\Omega }}}_{{q}_{2}}^{{q}_{1}}$, has the ability to change the weight of an error operator, ${E}_{{q}_{1}}^{i}\otimes {{\mathbb{1}}}_{{q}_{2}}$, such that

$$\begin{eqnarray}&&{{\rm{\Omega }}}_{{q}_{2}}^{{q}_{1}}\,\bullet \,({E}_{{q}_{1}}^{i}\otimes {{\mathbb{1}}}_{{q}_{2}})\,\bullet \,{({{\rm{\Omega }}}_{{q}_{2}}^{{q}_{1}})}^{\dagger }=({E}_{{q}_{1}}^{j}\otimes {E}_{{q}_{2}}^{k}),\end{eqnarray} \tag{ 19 }$$

where q₁ and q₂ are the control and target qubits respectively, and E^i,j,k are non-identity elements of the single-qubit Pauli group. As both ${E}_{{q}_{1}}^{i}\otimes {{\mathbb{1}}}_{{q}_{2}}$ and ${E}_{{q}_{1}}^{j}\otimes {E}_{{q}_{2}}^{k}$ are Pauli group operators, we see that ${{\rm{\Omega }}}_{{q}_{2}}^{{q}_{1}}$ must be a Clifford gate (for an overview of the Clifford group see appendix B). CPC quantum memories can be described entirely in terms of Clifford gates, as their operations are restricted to manipulating stabiliser states. This allows for efficient classical simulation. For an example of such a simulation, see the CPC syndrome calculation algorithm we outline in appendix C.

Another way of thinking about the CPC interaction gates is in terms of entanglement. In equation (19), it can be seen that the general CPC gate de-localises error information from the control to the target, suggesting the operation has the potential to entangle states. Furthermore, we know that elements of the two-qubit stabiliser states are either maximally entangled or separable. Any Clifford entangling gate that maps between these states, and therefore any CPC interaction, is a maximally entangling operation.

We have now established that CPC gates must be maximally entangling Clifford operations. However, many experiments will have native gates that do not satisfy these requirements. For example, several qubit technologies have a native interaction of the form $\sqrt{{\rm{SWAP}}}$ [41], which is only partially entangling. In these circumstances, multiple applications of the native gate, in addition to local operations, are required to synthesise the desired maximally entangling behaviour. It is typically the case that quantum computing experiments will have different error rates for single-qubit and two-qubit gates [42]. Circuit compilation strategies should therefore aim to minimise the gate type with the highest error rate. In the case of ion traps, for example, the two-qubit gates have lower fidelities than single-qubit gates [11, 43].

We will now outline general CPC circuit simplification procedures for maximally entangling Clifford gates. It can be shown that all Clifford entangling gates are local Clifford equivalent to either the ${\rm{CZ}}$ or the CZ-SWAP interaction. With this knowledge, we can write all maximally entangling Clifford gates in terms of a central kernel, containing either a ${\rm{CZ}}$ or CZ-SWAP interaction, supplemented by local Clifford gates (see figure 17(a)).

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The single-qubit Clifford group is generated by P and H gates. Any native gate can therefore be constructed from its by kernel via the addition of local gates generated from combinations of P and H. The P gates can be trivially pushed through the ${\rm{CZ}}$ kernel. Likewise, it is possible to push P gates through the ${\rm{CZ}} \mbox{-} {\rm{SWAP}}$ kernels, although the effect of the ${\rm{SWAP}}$ gate must be taken into account.

In section 6.3 we demonstrated the compilation of a CPC code using the SP native gate, which is local Clifford equivalent to a ${\rm{CZ}}$ gate. The exact transformation from ${\rm{CZ}}$ kernel to SP gate is shown in figure 17(b). As the local operations in this case consist of P^†gates, we have the freedom move P gates through the SP native gate. Hadamard gates H, however, restrict movement, but in many cases will cancel when the native gate is compiled into a CPC circuit.

The general procedure for compiling a CPC code with a given native gate can now be written as follows. First, eliminate any unnecessary H gates by identifying cancellations between adjacent CPC gates. Second, determine the behaviour when P gates are pushed through the native gate. As all maximally entangling Clifford gates have either a ${\rm{CZ}}$ or CZ-SWAP kernel, it is often possible to trivially move P gates through each block of the encoder. Once these simplifications rules have been established, they can be applied systematically to substantially reduce the CPC circuit gate count.

The idealised ion trap we are considering has seven application qubits. We assume that during the wait stage the ion trap qubits are subject to a biased depolarising noise channel of the form

$$\begin{eqnarray}&&{ \mathcal E }[\rho ]=(1-{p}_{x}-{p}_{z}-{p}_{x}{p}_{z})\rho +{p}_{x}X\rho X+2{p}_{x}{p}_{z}Y\rho Y+{p}_{z}Z\rho Z,\end{eqnarray} \tag{ 20 }$$

where ρ is the single-qubit density matrix, and p_x and p_z are the probabilities of X and Z errors respectively. This error model assumes the ion trap has independent error mechanisms for X and Z errors, but Y errors occur only as a result of successive single-qubit errors of the form XZ and ZX¹ . Similar error models have recently been considered in [44, 45]. For the purposes of our ion trap model, we assume that the error probabilities p_x and p_z are low enough that the probability of Y errors becomes negligibly small. The effective error model can then be written as

$$\begin{eqnarray}&&{ \mathcal E }[\rho ]\approx (1-{p}_{x}-{p}_{z})\rho +{p}_{x}X\rho X+{p}_{z}Z\rho Z.\end{eqnarray} \tag{ 21 }$$

Under the above error model for the idle ion trap qubits, the CPC quantum memory only needs to correct X and Z errors. We choose this noise model for our proof-of-concept outline of the CPC design process, as it corresponds to the simplest possible non-classical error model. Our aim is to discover non-degenerate quantum codes which produce a unique syndrome for single X and Z errors on any of the seven qubits in the trap.

The maximum possible encoding density of a non-degenerate QEC code is constrained by the quantum Hamming bound, which states that an [[n, k, d]] code must satisfy the following inequality

$$\begin{eqnarray}&&\displaystyle \sum _{j=0}^{(d-1)/2}\left(\displaystyle \genfrac{}{}{0em}{}{n}{j}\right)| { \mathcal E }{| }^{j}\ {2}^{k}\leqslant {2}^{n},\end{eqnarray} \tag{ 22 }$$

where $| { \mathcal E }|$ is the size of the single-qubit error set [9]. As we are considering only X and Z errors in the generic ion trap under the error model described by equation (21), the size of the error set is $| { \mathcal E }| =2$. Under this error model, the quantum Hamming bound tells us that the maximum number of data qubits that can be encoded in 7 physical qubits is k_max = 3. The optimal 7 qubit CPC code will therefore be of the form [[n = 7, k = 3, d = 3]]. Note that the code distance is d = 3, indicating that these [[7, 3, 3]] codes will be able to correct one error per CPC cycle.

An advantage of the CPC framework lies in the fact that new instances of such optimal codes can be discovered numerically, either using brute-force or more sophisticated optimisation techniques [3]. We now demonstrate these strategies in practice, by showing how optimal [[7, 3, 3]] CPC codes can be discovered via exhaustive search.

A [[7, 3, 3]] CPC code has k = 3 data qubits and n − k = 4 parity qubits. The adjacency matrices therefore have the form

$$\begin{eqnarray}{{m}}_{b} & = & \left(\begin{array}{cccc}{b}_{11} & {b}_{12} & {b}_{13} & {b}_{14}\\ {b}_{21} & {b}_{22} & {b}_{23} & {b}_{24}\\ {b}_{31} & {b}_{32} & {b}_{33} & {b}_{34}\end{array}\right),\quad {{m}}_{p}=\left(\begin{array}{cccc}{h}_{11} & {h}_{12} & {h}_{13} & {h}_{14}\\ {h}_{21} & {h}_{22} & {h}_{23} & {h}_{24}\\ {h}_{31} & {h}_{32} & {h}_{33} & {h}_{34}\end{array}\right),\\ {{m}}_{c} & = & \left(\begin{array}{cccc}0 & {c}_{12} & {c}_{13} & {c}_{14}\\ 0 & 0 & {c}_{23} & {c}_{24}\\ 0 & 0 & 0 & {c}_{34}\\ 0 & 0 & 0 & 0\end{array}\right),\end{eqnarray} \tag{ 23 }$$

where b_xy, h_xy, c_xy are binary values. New CPC circuits can be made by generating different instances of these matrices. The single-qubit error syndrome table for each code can be calculated efficiently using a stabiliser simulator or the algorithm we describe in appendix C. If the set of syndromes is unique, the respective matrices represent a valid [[7, 3, 3]] code.

The number of possible combinations of the adjacency matrices for CPC circuits of type [[7, 3, d = ?]] is 2³⁰. By an exhaustive search, we have discovered that 306, 480 of these permutations (0.03% of the search space) are working [[7, 3, 3]] codes. These codes have distance d = 3, and produce unique syndromes for all single-qubit X and Z errors across the seven qubits. Of the discovered set, there are 2190 symmetry-inequivalent codes that cannot be transformed from one to another by rearranging the qubit order. However, some symmetry-equivalent code permutations are more amenable to circuit optimisation than others. We will therefore continue to consider the entire set of 306, 480 codes in the CPC design process.

Now that a set of [[7, 3, 3]] circuits has been found, the next stages in the CPC design process involves analysis to determine which one of the 306, 480 codes is best suited for implementation on the ion trap device. Figure 18 shows a histogram of the discovered [[7, 3, 3]] codes, binned by the combined number of ${\rm{CNOT}}$ gates and conjugate-propagator gates in their encoder. This quantity will be referred to as the CPC gate count, and can be determined by counting the number of non-zero entries across the three adjacency matrices.

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In ion trap hardware, inter-qubit operations are typically the most expensive gate type in terms of their potential to introduce errors [11, 43]. As a result, the CPC circuits with the lowest CPC gate count are most desirable. In the set of [[7, 3, 3]] codes, the shortest circuit encoders have 14 CPC gates. This is a 22% reduction in circuit depth compared to the median gate count of 18. The number of [[7, 3, 3]] circuits with the minimum encoder depth of 14 is 864 of which 245 are symmetry inequivalent. Further work is therefore necessary to narrow down the code set, and find the optimum quantum memory for the ion trap device.

The encoder length statistics for the [[7, 3, 3]] CPC codes are summarised in table 3. Note that in this simple first analysis, we have not accounted for any of the constraints imposed by the ion trap's nearest-neighbour requirement for two-qubit operations. In the next section, we outline how the [[7, 3, 3]] codes can be compiled in such a setting through the introduction of additional ${\rm{SWAP}}$ gates.

The results in this section demonstrate that the CPC framework provides constructive tools for discovery of optimal [[7, 3, 3]] codes that saturate the quantum Hamming bound. Furthermore, the search was performed using a simple brute-force technique that requires only a basic knowledge of the CPC code structure to implement. The Python script used to perform the code search is approximately 200 lines long, and required approximately 4 days to run on a CPU clocked at 3.2 GHz with 8Gb of RAM.

The second stage of the CPC design process involves selecting codes to meet the demands of the chosen quantum hardware and its qubit layout. Figure 19(a) shows the idealised model ion trap under consideration, labelled with 3 data qubits and 4 parity qubits as required by the [[7, 3, 3]] code. Under the restriction of nearest-neighbour connectivity, interactions between spatially separated qubits can still be realised by performing ${\rm{SWAP}}$ operations. For example, interacting qubit B with p₁ would first require a ${\rm{SWAP}}$ gate between qubits B and C, or qubits C and p₁. Circuits with fewer long range interactions will require fewer ${\rm{SWAP}}$ gates, and will therefore have a reduced two-qubit gate count.

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There are a number of strategies for calculating the sequences of ${\rm{SWAP}}$ operations required to compile a CPC circuit on a nearest-neighbour architecture. Here we adopt a simple approach in which qubits are always swapped in the upwards direction. As an example of this, in figure 19(b), qubit p₁ is swapped upwards, instead of qubit B being swapped downwards. More advanced ${\rm{SWAP}}$ compilation strategies, that combine upwards and downwards moves, can yield circuits with lower ${\rm{SWAP}}$ counts. However, such analysis is computationally expensive, and can impose a bottleneck in the CPC design process. By restricting our approach to upwards ${\rm{SWAP}}$ moves only, an exhaustive search of the [[7, 3, 3]] CPC codes remains possible.

Figure 20 shows the histogram of the ${\rm{SWAP}}$ compiled [[7, 3, 3]] codes distributed by the total two-qubit gate count (CPC gates + ${\rm{SWAP}}$ gates). The optimum [[7, 3, 3]] CPC code with the shortest encoder is shown in figure 21(b). The encoder for this circuit includes 14 CPC gates, and requires an additional 13 ${\rm{SWAP}}$ operations to be implemented on a linear, nearest-neighbour architecture. The depth of the encoder, in terms of the number of two-qubit gates, is therefore 27. For comparison, the un-compilied version of this [[7, 3, 3]] code is shown in figure 21(a).

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The results of two-qubit gate count analysis for the [[7, 3, 3]] codes, following compilation onto the nearest-neighbour hardware, are summarised in table 4. The optimum circuit has an encoder length of 27, compared to the median of 51, a 47% reduction in circuit gate count. Only one CPC code was discovered with the minimum encoder length. The CPC circuit optimisation, with regards to qubit layout, can therefore be considered complete.

Table 4.  Summary of the gate-count statistics for the set of [[7, 3, 3]] codes following the ${\rm{SWAP}}$ gate compilation. The two-qubit gate count is defined as the number of CPC gates + ${\rm{SWAP}}$ gates. The depth reduction is the percentage decrease in gate count of the smallest circuit relative to the median.

Encoder gate length (number of two-qubit gates)
Mininum	Median	Depth reduction
27 (1 discovered)	51	47%
Optimum code:
Encoder length = 27 gates; no. CPC gates = 14; no. ${\rm{SWAP}}$ gates = 13

The ion trap under consideration has a native gate that resembles the SP gate introduced in section 4. The final stage of the CPC design process involves systematically applying the SP simplification procedures described in section 5.1 to each of the 306, 480 discovered CPC codes. The compilation efficiency of a given code can be quantified by counting the number of local gates that remain in the simplified circuit. The optimal code for the ion trap device is then identified as the circuit with the shortest total encoder length, defined by

$$\begin{eqnarray}&&{{ \mathcal L }}_{\mathrm{CPC}}=| \ \mathrm{CPC}| +| \ \mathrm{SWAP}| +| \ \mathrm{LOCAL}| ,\end{eqnarray} \tag{ 24 }$$

where $| \ \mathrm{CPC}|$ is the CPC gate count, $| \ \mathrm{SWAP}|$ is the ${\rm{SWAP}}$ gate count and $| \ \mathrm{LOCAL}|$ is the local gate count.

Table 5 summarises the simplification statistics for the local gate counts when the [[7, 3, 3]] CPC codes are compiled with the SP native gate. Without applying any simplifications, the median local gate count is 92. After applying the simplification routine, the median is 10, an 89% reduction in gate count.

The compiled [[7, 3, 3]] CPC circuit with the lowest local gate count after simplification is shown in figure 22. This circuit is compiled from the CPC code with the lowest two-qubit gate count, as discovered in the last subsection and depicted in figure 21. We can therefore identify the compiled [[7, 3, 3]] code in figure 22 as the optimum code for our device with a total gate count of ${{ \mathcal L }}_{\mathrm{CPC}}=34$. For comparison, the median total gate count across all 306, 480 CPC codes was ${{ \mathcal L }}_{\mathrm{CPC}}=61$. The total reduction in circuit depth for the optimised circuit relative to the median is therefore 44%. Note that it will not always be the case that the circuit with the lowest two-qubit gate count will also be the circuit that compiles most efficiently. For this reason, the entire discovered set of [[7, 3, 3]] CPC codes were considered in stage 3 of the design process, rather than restricting the analysis to the single code identified in stage 2.

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